No abstract

Abstract1 -A novel imaging technique is proposed for fully digital detection of phase and intensity of light. A fully integrated camera implementing the new technique was fabricated in a 0.35μm CMOS technology. When coupled to a modulated light source, the camera can be used to accurately and rapidly reconstruct a 3D scene by evaluating the time-offlight of the light reflected by a target. In passive mode, it allows building differential phase maps of reflection patterns for image enhancement purposes. Tests show the suitability of the technique and confirm phase accuracy predictions.

No abstract

Abstract1 -A novel imaging technique is proposed for fully digital detection of phase and intensity of light. A fully integrated camera implementing the new technique was fabricated in a 0.35μm CMOS technology. When coupled to a modulated light source, the camera can be used to accurately and rapidly reconstruct a 3D scene by evaluating the time-offlight of the light reflected by a target. In passive mode, it allows building differential phase maps of reflection patterns for image enhancement purposes. Tests show the suitability of the technique and confirm phase accuracy predictions.

Abstract. Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.