Compiling to FPGAs via an EPIC compiler's intermediate representation

Abstract

The increasing density and speed of modem j e l d programmable gate arrays ofer the reconjgurable systems using them greater capability andJ7exibili!y, in particular for more complex computation. However, there remains a vely important problem of how to design on a more abstract level to manage the vast hardware resource and shorten the design time. This paper presents an approach to compile a system level description to hardware through a conventional so/hvare intermediate representation (IR) of a state-of-the-art optimizing compiler for Explicitly Parallel Insmction Computing (EPIC) processors. The front end compiles C progrms into an intermediate representation for an injnite resource EPIC processor. The intermediate representation contains all the information of confrolJ7ow graph of basic blocks. It is /i.m this intermediate representation that we have devised means to generate synthesizable Register Transfer level (RTL-level) Verilog description that can be mapped info the reconjgurable HWdevice. We will describe the details of the translation process and the performance on actual FPGA hardware.