On an external memory scheme for processor arrays

Abstract

Abstract:The problem of generating memory interfaces between loop-based accelerators and external memory is gaining the attention from the high-level synthesis research community. This paper presents an external memory system for inserting/extracting data to/from a loop-based accelerator derived by a high-level synthesis approach. The memory system is composed by four architectural cases which could occur during hardware synthesis. The memory system is based on a global asynchronous local synchronous approach and the use of dualport memory banks. FPGA-based implementation results show that the proposed memory system is technologically achievable and provides a high-bandwidth without introducing communication overhead.

Processor arrays generation for matrix algorithms used in embedded platforms

“…⊂ ℤ and ⊂ ℤ 2 , respectively. After these transformations, the controller [7,8,15], the processor array topology [16,17], the PE data-path [7,8] and the memory controller [10,18] are synthesized (Figure 1.c). The controller indicates when a PE inside the processor array must be activated at a given time, and which operation must be performed inside of the PE.…”

“…Figure 4 exemplifies the internal architecture of two of these four cases. A more detailed explanation of the complete memory system could be found in [18]. Figure 5 shows the block diagram integrating the processor array data-path, the controller, and the memory system.…”