High k Dielectrics on High-Mobility Substrates: The Interface!

Abstract

To reduce power consumption from gate oxide leakage, Intel Corporation has successfully introduced high-k dielectrics for 45 nm CMOS technology. This paper provides an overview of interface defect response at the high-k dielectric and high-mobility substrate interface. Different passivation methods are discussed, as are their influence on device performance. The impact of the deposition process is also discussed. The influence of deposition parameters, substrate surface orientation, pre-deposition surface treatment, and subsequent annealing temperatures on interface characteristics is presented. The development of high k/Ge and high k/III-V interfaces are also discussed.

Ambipolar operation of progressively designed symmetric bidirectional transistors fabricated using single-channel vertical transistor and electrochemically prepared copper oxide

“…These curves provide information about the absence or presence of hole and electron paths along the channel on the sidewall controlled by the artificial plasma. 58–60 The non-post-treated reference p-type channel V-Tr exhibits accumulation and depletion modes like those of the majority carriers at low and high frequencies, wherein the majority-carrier-driven transistor does not exhibit the usual n-type characteristics owing to the absence of strong inversion in the channel. 61 Therefore, the accumulated-hole contribution leads to a considerable capacitance of ∼2.1 nF cm −2 in the negative bias region, wherein the holes are amplified at both low and high frequencies.…”

Gate stack dielectric degradation of rare-earth oxides grown on high mobility Ge substrates

“…The back ohmic contact was made using eutectic InGa alloy. The further experimental (deposition techniques, characteristics) details on CeO 2 , Dy 2 O 3 , and La 2 O 3 have been described in detail and elaborately in our previous work 1, 6,13,18,23,28 together with their corresponding gate stacks with HfO 2 on Ge.…”

“…6,18,27,28 However, in terms of reliability, when gate stacks of high-j dielectrics are used in MOS devices they produce current decay behaviour, (decay transient of J g -t) which is defined as Maxwell-Wagner instabilities (M-W). 7,15,29 This M-W model, can explain the experimental results (J g -t) under certain limitations: (a) until a certain stress time (i.e., t stress 100 s) (b) when the M-W current (J MW ) is very low and dominated mainly by the so called Curie-von Schweilder (C-S) relaxation current (c) at low CVS regime.…”

“…Moreover, the interface traps play a crucial role on the dielectric degradation and the electrical instabilities. 6 In high-k dielectrics, the gate stack itself causes charge accumulation and exhibits a decay current transient behavior. This current decay behavior can be explained by means of the so called Maxwell-Wagner (M-W) instability, 7 named as one of the major drawbacks of gate stack technology since it hinters the passivation quality of the high mobility substrates surface, e.g., Ge.…”

Positive charge trapping phenomenon in n-channel thin-film transistors with amorphous alumina gate insulators

“…[6][7][8] In 2007, high-k dielectrics have entered the silicon electronics industry with the aim to reduce the power dissipation in MOSFETs. 9 In the meantime, they have gained popularity for high mobility semiconductors such as Ge and III-V, 10 oxide semiconductors, 11 and organic semiconductors. 12 Nevertheless, their larger ionic bonding character compared to SiO 2 results in an increased number of interface and intrinsic defects, especially oxygen vacancies (V O ), 13 which are highly susceptible to charge trapping.…”