High-frequency FinFET model

Wang, J.; Hutchens, Chris; Popp, J.D.; Rowland, Jason; Zhang, Y.

doi:10.1049/el:20057665

Cited by 13 publications

(8 citation statements)

References 4 publications

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“…Figure 6(a) compares the peak f T values predicted by our simulation with the ITRS targets and published experimental data for NMOS, SOI devices and FinFETs. Simulated f T values for planar SOI MOS devices reasonably fit the trend pattern of the experimental data [6][7][8][9][17][18][19][20][21][22][23][24][25][26][27][28][29][30] for planar MOSFETs published in the literature. New materials such as strained silicon could be used to achieve higher values of the drive current and cut-off frequency for nanoscale MOSFETs.…”

Section: Comparative Analysis Of Multi-gate Devicessupporting

confidence: 68%

“…In a DG FinFET design, the top gate is electrically isolated from the body resulting in a gate width of 2H fin instead of 2H fin + T fin for a TG structure, where H fin and T fin are the height and thickness of the silicon fin, respectively [4]. Although some work has been published on dc characteristics of FinFETs arguing on the feasibility of keeping the top gate electrically isolated [5,6] at nanoscale regimes, very few papers [7][8][9] have reported the rf performance of these non-classical vertical MOS devices.…”

Section: Introductionmentioning

confidence: 99%

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Comparative analysis of nanoscale MOS device architectures for RF applications

Kranti¹,

Armstrong²

2007

Semicond. Sci. Technol.

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The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. It is shown that although nanoscale FinFETs achieve higher values of intrinsic dc gain (nearly 20 dB higher than planar SG devices), they also present higher gate capacitance that severely undermines their rf performance. We also show that at large values of drain currents, well-designed conventional planar single and double gate SOI MOSFETs attain higher values of cut-off frequency compared to FinFETs, whereas at lower drain currents, a well-aligned planar double gate SOI MOSFET is the optimal structure. The reason for higher parasitic capacitance in FinFETs as compared to planar MOSFETs is examined in detail. An assessment of the impact of back gate misalignment on the rf performance of a 25 nm gate length planar double gate MOSFET indicates that a misalignment of 12 nm towards the source end is acceptable to give superior performance to a FinFET. The importance of source/drain extension region engineering in nanoscale FinFETs for ultra-low voltage analogue applications is also investigated. RF figures of merit for planar and vertical MOS devices are also compared based on layout-area calculations. The paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical MOSFETs.

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Section: Comparative Analysis Of Multi-gate Devicessupporting

confidence: 68%

Section: Introductionmentioning

confidence: 99%

Comparative analysis of nanoscale MOS device architectures for RF applications

Kranti¹,

Armstrong²

2007

Semicond. Sci. Technol.

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“…Microwave small-signal characterizations of FinFETs have been recently presented by Wang et al 8 and Lederer et al 9 Wang et al 8 presented a small-signal rf model of Fin-FET, whereas Lederer et al 9 gave device measurements showing that the transition frequency ͑f T ͒ and unit power gain frequency ͑f max ͒ can reach 40 and 80 GHz, respectively, for a 100 nm gate length FinFET. A more recent paper has presented 50 nm gate length FinFET measurements predicting an f max of 250 GHz with an optimized process.…”

Section: Introductionmentioning

confidence: 99%

High frequency and noise model of gate-all-around metal-oxide-semiconductor field-effect transistors

Nae

Lázaro

Iñíguez

2009

Journal of Applied Physics

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Articles you may be interested inThreshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor J. Appl. Phys. 112, 024513 (2012); 10.1063/1.4737779 Kubo-Greenwood approach for the calculation of mobility in gate-all-around nanowire metal-oxide-semiconductor field-effect transistors including screened remote Coulomb scattering-Comparison with experiment Model of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 100, 033501 (2012); 10.1063/1.3678023 High-frequency compact analytical noise model for double-gate metal-oxide-semiconductor field-effect transistor J. Appl. Phys. 105, 034510 (2009); 10.1063/1.3077279Theoretical consideration for carrier transport noise in nonequilibrium steady-state operation of metal-oxide-semiconductor field-effect transistorThe surrounding gate ͑SGT͒ metal-oxide-semiconductor field-effect transistor is one of the most promising candidates for the downscaling of complementary metal-oxide-semiconductor technology toward the sub-50-nm channel length range since the SGT architecture allows excellent control of the channel charge in the silicon film, thus reducing short channel effects. However, at these dimensions, quantum effects must be considered in order to develop accurate compact models useful for circuit simulations. In this paper we study the influence of quantum effects on dc, radio frequency ͑rf͒, and microwave noise for nanoscale SGT transistors including nonstationary effects. We present an analytical charge model for adjusting the charge control computed from the self-consistent solution of the two-dimensional Schrödinger and Poisson equations. rf and noise performances are calculated using the active transmission line method. We compared, on the one hand, classical and quantum charge control models and, on the other, drift-diffusion and hydrodynamic transport models.

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“…Finally, we focus on extraction of the small‐signal equivalent circuit. Many studies have proposed accurate modeling procedures for extracting equivalent circuits of microwave transistors . On the basis of these studies, we propose an innovative model extraction method and verify this method with measured data.…”

Section: Introductionmentioning

confidence: 99%

“…Many studies have proposed accurate modeling procedures for extracting equivalent circuits of microwave transistors. [6][7][8][9][10][11][30][31][32][33][34] On the basis of these studies, we propose an innovative model extraction method and verify this method with measured data. In this study, a physical-based compact small-signal ECM and its extraction methodology are presented.…”

Section: Introductionmentioning

confidence: 99%

A broadband small‐signal model extraction methodology over 0.2‐220 GHz for bulk FinFETs in RF CMOS technology

Zhou

Liu

Chen

et al. 2020

Int J Numerical Modelling

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This study presents a physical‐based broadband radio frequency (RF) small‐signal equivalent circuit model (ECM) for triple‐gate (TG) bulk fin field‐effect transistors (FinFETs) and its extraction methodology. To increase model accuracy and extend the effective frequency band, substrate effect, test ground‐signal‐ground (G‐S‐G) pads, and metal interconnection parasitics are considered together in the transistor model. All the elements in the model are extracted from a combination of analysis and physical equations using multibias scattering parameters. On the basis of the proposed model, the simulation results correspond to the measured results in the frequency range from 200 MHz to 220 GHz without any complex fitting or optimization steps.

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High-frequency FinFET model

Cited by 13 publications

References 4 publications

Comparative analysis of nanoscale MOS device architectures for RF applications

Comparative analysis of nanoscale MOS device architectures for RF applications

High frequency and noise model of gate-all-around metal-oxide-semiconductor field-effect transistors

A broadband small‐signal model extraction methodology over 0.2‐220 GHz for bulk FinFETs in RF CMOS technology

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