No abstract
This paper presents a fault tolerant design technique for clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless wave pipeline [12] which is ideally supposed to yield the theoretical maximum performance. Request signal is the most critical component for the clockless control of the wave pipelined processing of data. In practice, the request signal is very sensitive and vulnerable to electronic crosstalk noise, referred to as glitch, and this problem has become extremely stringent in the ultra-high density integrated circuits today. Electronic crosstalk noise may devastate the operational confidence level of the clockless wave pipeline. In this context, this paper characterizes the yield and reliability properties of the two-phase clockless asynchronous pipeline with respect to glitch. Based on the yield and reliability characterization, a simple yet effective fault tolerant architecture by using redundant request signals is proposed. The reliability model evaluates the impact of the request signal glitch on the overall reliability, and can be used to maneuver the proposed fault tolerant architecture. An experimental simulation is conducted to demonstrate the efficiency and effectiveness of the proposed fault tolerant technique.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.