High density optical and electrical interfaces for chip-scale silicon photonic receiver

Takemura, Koichi; Ibusuki, Yasuhiro; Ukita, Akio; Kurihara, Minoru; Kinoshita, Keizo; Okamoto, Daisuke; Fujikata, Junichi; Yashiki, Kenichiro; Suzuki, Yoshishige; Horikawa, Tsuyoshi; Mogami, Tohru; Kurata, K.

doi:10.23919/icep.2017.7939369

Cited by 6 publications

(2 citation statements)

References 16 publications

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“…Among them, Ayar Labs is using angle polished gradient index fibers to reduce the thickness of the module and PETRA is using optical pins. This works are detailed in references [161] and [162].…”

Section: Fiber Packagingmentioning

confidence: 99%

Silicon photonics for terabit/s communication in data centers and exascale computers

Bernabé

Wilmart

Hasharoni³

et al. 2021

Solid-State Electronics

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Section: Fiber Packagingmentioning

confidence: 99%

Silicon photonics for terabit/s communication in data centers and exascale computers

Bernabé

Wilmart

Hasharoni³

et al. 2021

Solid-State Electronics

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“…Thus, a chip-to-board optical coupling interface that is alignment tolerant, energy efficient, and agnostic towards channel-density scaling can help push the case of realizing on-board chip-to-chip optical communication. So far, only a few research groups have reported integration schemes ranging from adiabatic optical coupling [7], [8] to cone-shaped optical pin coupling interface for multimode interconnections [9], [10]. As can be seen, all the approaches demonstrated before have used the device side of the chip to interface with a package or a board-level optical interconnect.…”

Section: Introductionmentioning

confidence: 99%

Ball Lens Embedded Through-Package Via To Enable Backside Coupling Between Silicon Photonics Interposer and Board-Level Interconnects

Mangal

Missinne

Campenhout

et al. 2020

J. Lightwave Technol.

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Development of an efficient and densely integrated optical coupling interface for silicon photonics based board-level optical interconnects is one of the key challenges in the domain of 2.5D/3D electro-optic integration. Enabling high-speed onchip electro-optic conversion and efficient optical transmission across package/board-level short-reach interconnections can help overcome the limitations of a conventional electrical I/O in terms of bandwidth density and power consumption in a highperformance computing environment. In this context, we have demonstrated a novel optical coupling interface to integrate silicon photonics with board-level optical interconnects. We show that by integrating a ball lens in a via drilled in an organic package substrate, the optical beam diffracted from a downward directionality grating on a photonics chip can be coupled to a board-level polymer multimode waveguide with a good alignment tolerance. A key result from the experiment was a 14 µm chipto-package 1-dB lateral alignment tolerance for coupling into a polymer waveguide with a cross-section of 20×25 µm 2 . An in-depth analysis of loss distribution across several interfaces was done and a -3.4 dB coupling efficiency was measured between the optical interface comprising of output grating, ball lens and polymer waveguide. Furthermore, it is shown that an efficiency better than -2 dB can be achieved by tweaking few parameters in the coupling interface. The fabrication of the optical interfaces and related measurements are reported and verified with simulation results.

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Vertical Optical and Electrical Interconnection for Chip-Scale-Packaged Si Photonic Transceivers

Takemura

Ukita

Ibusuki

et al. 2019

2019 International 3D Systems Integration Conference (3DIC)

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High density optical and electrical interfaces for chip-scale silicon photonic receiver

Cited by 6 publications

References 16 publications

Silicon photonics for terabit/s communication in data centers and exascale computers

Silicon photonics for terabit/s communication in data centers and exascale computers

Ball Lens Embedded Through-Package Via To Enable Backside Coupling Between Silicon Photonics Interposer and Board-Level Interconnects

Vertical Optical and Electrical Interconnection for Chip-Scale-Packaged Si Photonic Transceivers

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