High density interconnect at 10&amp;#x00B5;m pitch with mechanically keyed Cu/Sn-Cu and Cu-Cu bonding for 3-D integration

Reed, Jason D.; Lueck, Matthew; Gregory, Chris; Huffman, Alan; Lannon, John; Temple, Dorota

doi:10.1109/ectc.2010.5490704

Cited by 29 publications

(15 citation statements)

References 5 publications

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“…TSVs built using Via-last technology are preferred for active interposers as the active devices can be manufactured in the foundry end and the wafers can be passed to OSATs or other lower cost packaging houses for TSV manufacturing and assembly. The impact of TSV-last 146 technology on the transistor performance 147,148 should be evaluated as well. Moreover, as 2.5D TSI technology would be catering to sensor as well as optical technologies co-existing with 2.5D electrical systems, the process integration schemes to accomplish such integration will be developed.…”

Section: Metal-metal Bondingmentioning

confidence: 99%

See 1 more Smart Citation

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

124

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Section: Metal-metal Bondingmentioning

confidence: 99%

“…[147][148][149] The work carried out by Lin et al, wherein solder paste reflow or electroplated Cu is applied with fan-out configuration for Comic-Con International (CCI). However, this approach is more focused on low-cost manufacturing process than scaling down of the interconnect pitch.…”

mentioning

confidence: 99%

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

124

View full text Add to dashboard Cite

“…In recent years, research on TSV technologies has been widely reported, and various micro-bump technologies have also been studied for chip stacking. [2][3][4] However, fine pitch 3D chip stacks for thin die still faces many challenges including handling of the thin die, interconnect materials, process control to achieve high yield with high reliability. In addition, handling of chips as thin as 100μm or less thickness requires novel tooling and processes because thin chips are much fragile and may not remain planar compared to conventional chips as 750μm thickness.…”

Section: ι Introductionmentioning

confidence: 99%

Fabrication and bonding process of fine pitch Cu pillar bump on thin Si chip for 3D stacking IC

Kang

Yoo

et al. 2012

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International

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Abstracts3D packaging technology has been studied actively due to requirement of high performance, high density, and multifunction on electronic devices. This study investigated formation and bonding process of ultra-fine Cu pillar bump on both sides of Si thin wafer for 3D IC. Thickness of the thin wafer was 100μm. The bumps for the interconnection were formed as Sn-3.5Ag cap bump on Cu pillar bump by electroplating method. The diameter and height of the bump were 20μm, respectively. Thin Si chip was joined at bonding load 1.5N and bonding temperature 260°C by flip-chip bonder and then reflow process was added for 15~20 seconds at 260°C. After reflow process, thickness of IMCs in the Sn/Cu pillar interface was nearly the same compared with only flip-chip bonding method. And the effect of self-alignment was found.

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“…[1][2][3][4][5] Also, 3D integration technology makes it possible to stack heterogeneous systems. [4][5][6] A wire-bonding method has been widely used to interconnect stacked chips. This method has several disadvantages such as long connection length, deterioration of high frequency characteristics, and limited connection between chips.…”

Section: Introductionmentioning

confidence: 99%

Chip to Chip Bonding Using Cu Bumps Capped with Thin Sn Layers and the Effect of Microstructure on the Shear Strength of Joints

Kim

Woo

Kim

2014

Journal of Elec Materi

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Chip to chip bonding techniques using Cu bumps capped with thin solder layers have been frequently applied to 3D chip stacking technology. We studied the effect of joint microstructure on shear strength. Joints were formed by joining Sn/Cu bumps on a Si die and Sn/Cu layers on another Si die at 245-330°C using a thermo-compression bonder. Three different types of microstructures were fabricated in the joints by controlling the bonding temperature and time, (1) a Sn-rich phase with a Cu 6 Sn 5 phase at the Cu interfaces, (2) a Cu 6 Sn 5 phase in the interior with a Cu 3 Sn phase at the Cu interfaces, and (3) one single Cu 3 Sn phase throughout the whole joint. The joint having a single Cu 3 Sn phase had the highest shear strength. Specimens were aged up to 2000 h at 150°C and 180°C. During aging, the microstructures of all joints were transformed in a single Cu 3 Sn phase. The shear strength of the joints was very sensitive to the formation of Cu 3 Sn and microvoids. Microvoids formed in the solder joints with a Cu 6 Sn 5 phase with and without a Sn-rich phase during aging and decreased the shear strength of the joints. Conversely, aging did not induce the formation of microvoids in the joints which originally had only a Cu 3 Sn phase and the shear strength was not decreased.

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High density interconnect at 10µm pitch with mechanically keyed Cu/Sn-Cu and Cu-Cu bonding for 3-D integration

Cited by 29 publications

References 5 publications

Heterogeneous 2.5D integration on through silicon interposer

Heterogeneous 2.5D integration on through silicon interposer

Fabrication and bonding process of fine pitch Cu pillar bump on thin Si chip for 3D stacking IC

Chip to Chip Bonding Using Cu Bumps Capped with Thin Sn Layers and the Effect of Microstructure on the Shear Strength of Joints

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