Fabrication and bonding process of fine pitch Cu pillar bump on thin Si chip for 3D stacking IC

Abstract

Abstracts3D packaging technology has been studied actively due to requirement of high performance, high density, and multifunction on electronic devices. This study investigated formation and bonding process of ultra-fine Cu pillar bump on both sides of Si thin wafer for 3D IC. Thickness of the thin wafer was 100μm. The bumps for the interconnection were formed as Sn-3.5Ag cap bump on Cu pillar bump by electroplating method. The diameter and height of the bump were 20μm, respectively. Thin Si chip was joined at bonding load 1.5N and bonding temperature 260°C by flip-chip bonder and then reflow process was added for 15~20 seconds at 260°C. After reflow process, thickness of IMCs in the Sn/Cu pillar interface was nearly the same compared with only flip-chip bonding method. And the effect of self-alignment was found.

Numerical analysis of thermo-mechanical characteristics of solder joint depending on change in solder junction structure of MCP

“…In particular, since a fine pitch size causes solder bridging, an existing junction structure has limitation in decreasing its package size. Recently Ki et al [10] has reported an ultra fine pitch Cu pillar bump with a solder cap bump on Cu pillar bump. This study indicates that a junction structure with an ultra fine pitch Cu pillar bump below 40 lm diameter for TSV (through Silicon via) and Chip-on-Chip (CoC) can solve the problems of a solder bridging phenomena and a low mechanical strength caused by low standoff height.…”

Thermo-Compression Bonding of Cu/SnAg Pillar Bumps with Electroless Palladium Immersion Gold (EPIG) Surface Finish

“…Recent improvements in performance and node size decrease in semiconductors lead to a lowering in the bump pitch of the semiconductor package [ 1 , 2 , 3 ]. The fine-pitch semiconductor packages have brought about a huge change in the flip-chip bonding process and materials.…”

Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

“…ICs are often the primary source of radiated emissions, and near field magnetic field can help engineers to track down EMI culprit and solve the . Three-dimensional stack-dies integrated circuits (3D-ICs) trend for vertical distance between ICs [16][17][18][19][20][21][22][23].…”