High density 3D fanout package for heterogeneous integration

Jeng, Shin-Puu; Chen, S. M.; Hsu, Feng-Cheng; Lin, Po-Yao; Wang, J. H.; Fang, T.; Kavle, Pravin; Lin, Y. J.

doi:10.23919/vlsit.2017.7998140

Cited by 3 publications

(3 citation statements)

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“…TSMC [144] proposed to use the FOWLP technology þ Cupillar/solder bump to eliminate the TSVs in the HBM cube. In the individual chip, the FOWLP is used to make the RDLs to fan-out all the circuitries to the peripherals of the package.…”

Section: Opportunities For Fan-out Wafer-level Packagingmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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Section: Opportunities For Fan-out Wafer-level Packagingmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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“…Recently, heterogeneous three-dimensional integrated circuit (3D-IC) technologies have been highlighted to dram- -atically increase transistor density without further scaling of the transistors themselves [11][12][13]. In addition, heterogeneous 3D-IC structures enable different functional die to be integrated into one systems-in-package without degrading performance [11,13]. In stacking die, throughsilicon vias (TSVs) should be formed on each die to transmit electrical signal or to deliver supplied power.…”

Section: Introductionmentioning

confidence: 99%

Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs

2021

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Through-silicon via (TSV)-induced mechanical stress and electrical noise coupling effects on sub 5-nm node nanosheet field-effect transistors (NSFETs) were investigated comprehensively compared to fin-shaped FETs (FinFETs) using TCAD for heterogeneous 3D-ICs. TSV-induced channel length directional stress (SZZ) predominantly causes variations of on-state current (ΔIon). NSFETs exhibit the greater ΔIon than FinFETs because electron velocities and densities in channels vary with respect to SZZ in the same directions for NSFETs but do the opposite for FinFETs. Nevertheless, TSV-induced mechanical stress is negligible when TSV is farther than keep-out zone. Meanwhile, TSV signals can be coupled to operating devices through substrate and induce capacitive and back-bias noise coupling currents (Icap, Ib-b). NSFETs exhibit the greater |Icap|/Ion than FinFETs because its wider source/drain (S/D) epitaxies form larger depletion capacitances between drain and punch-through stopper (PTS). On the other hand, the |Ib-b|/Ion is smaller for NSFETs because its parasitic bottom transistor alleviates back-bias-induced potential barrier lowering. Furthermore, wide diameter of Cu of TSV increases |Ib-b|/Ion only, but short rise time of TSV signals increases both |Icap|/Ion and |Ib-b|/Ion. Unfortunately, conventional devices cannot satisfy criterion for analog applications (|Icap, Ib-b|/Ion< 0.5%); therefore, a new strategy inserting bottom oxide (BOX) beneath the S/D with undoped PTS is suggested. The |Icap|/Ion for NSFETs decreases by undoped PTS, but not for FinFETs due to a remnant depletion capacitance between fin and PTS. The |Ib-b|/Ion for NSFETs decreases remarkably due to completely blocked Ib-b path, but FinFETs still have Ib-b path under the fin. Therefore, NSFETs with BOX and undoped PTS are the most suitable for sub 5-nm node heterogeneous 3D-IC, especially in analog applications.

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“…Several researchers discuss about maximum temperature and temperature rise time of a hotspot on LSI with a thinned Si base, and they suggest that the thermal characteristics and thickness of Si base show trade-off relationships. [17][18][19][20][21] Some researchers analytically investigated thermal problems in 3DS-ICs, [22][23][24] arising from more complex trade-off relationship of performance with further downscaling and increased current density by stacking. As for the transient thermal characteristics of thinned LSI, only a few research studies have been carried out on the macroscopic scale.…”

Section: Introductionmentioning

confidence: 99%

Investigation of transient thermal dissipation in thinned LSI for advanced packaging

Araga¹,

Shimamoto²,

Melamed³

et al. 2018

Jpn. J. Appl. Phys.

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Thinning of LSI is necessary for superior form factor and performance in dense cutting-edge packaging technologies. At the same time, degradation of thermal characteristics caused by the steep thermal gradient on LSIs with thinned base silicon is a concern. To manage a thermal environment in advanced packages, thermal characteristics of the thinned LSIs must be clarified. In this study, static and dynamic thermal dissipations were analyzed before and after thinning silicon to determine variations of thermal characteristics in thinned LSI. Measurement results revealed that silicon thinning affects dynamic thermal characteristics as well as static one. The transient variations of thermal characteristics of thinned LSI are precisely verified by analysis using an equivalent model based on the thermal network method. The results of analysis suggest that transient thermal characteristics can be easily estimated by employing the equivalent model.

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High density 3D fanout package for heterogeneous integration

Cited by 3 publications

References 0 publications

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs

Investigation of transient thermal dissipation in thinned LSI for advanced packaging

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