High-density 3D electronic-photonic integration

Stojanović, Vladimir; Settaluri, Krishna T.; Lin, Sen; Moazeni, Sajjad; Timurdogan, Erman; Sun, Chen; Moresco, M.; Su, Zhan; Chen, Y-H.; Leake, Gerald; LaTulipe, D.; McDonough, Colin; Hebding, Jeremiah; Coolbaugh, Douglas; Watts, Michael R.

doi:10.1109/e3s.2015.7336803

Cited by 4 publications

(5 citation statements)

References 6 publications

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Section: Electronic–photonic Co-packagingmentioning

confidence: 96%

“…A high-density 3D electronic–photonic integration with through-oxide technology where the SOI wafer is oxide bonded face-to-face with the CMOS wafer has also demonstrated a full 5 Gb/s chip-to-chip link over a 100 m single mode optical fiber. The electrical and optical energy consumption in this case is 560 fJ/bit and 4.2 pJ/bit respectively 2.5D Integration: This approach involves the integration of EICs and PICs on an interposer, which mediates electrical signals between the EIC and PIC as well as the external environment (PCB).…”

Section: Electronic–photonic Co-packagingmentioning

confidence: 99%

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Integrated Photonics Packaging: Challenges and Opportunities

et al. 2022

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Packaging of photonic integrated circuit (PIC) chips is an essential and critical step before they can be integrated into functional optoelectronic systems. Photonic packaging is however often a major barrier impeding scalable deployment of PIC technologies given its high cost and limited throughput. This perspective addresses the technical challenges and discusses promising strategies and research directions to overcome the "packaging bottleneck".

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Section: Electronic–photonic Co-packagingmentioning

confidence: 96%

Section: Electronic–photonic Co-packagingmentioning

confidence: 99%

Integrated Photonics Packaging: Challenges and Opportunities

et al. 2022

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“…In hybrid integration, the connection between the photonic chip and the electronic chip results in parasitics that limit the bandwidth and power consumption, such as the parasitic inductance (250 − 500 pH) and parasitic capacitance (~ 100 fF) caused by wire-bonding [108], as well as the parasitic capacitance (~ 30 fF) caused by micro-bump/copper pillar connection. However, 3D integration of electronic and photonic wafers performs with very low inter-connection parasitics capacitance (~ 3 fF) by through-oxide vias (TOVs) [109]. Monolithic integration reduces the parasitics of the wiring, improving the performance and increasing manufacturing costs.…”

Section: Statusmentioning

confidence: 99%

Co-packaged optics (CPO): status, challenges, and solutions

Tan

Liu³

et al. 2023

Front. Optoelectron.

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Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three-fourths of the datacenter traffic resides within datacenters. The conventional pluggable optics increases at a much slower rate than that of datacenter traffic. The gap between application requirements and the capability of conventional pluggable optics keeps increasing, a trend that is unsustainable. Co-packaged optics (CPO) is a disruptive approach to increasing the interconnecting bandwidth density and energy efficiency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics. CPO is widely regarded as a promising solution for future datacenter interconnections, and silicon platform is the most promising platform for large-scale integration. Leading international companies (e.g., Intel, Broadcom and IBM) have heavily investigated in CPO technology, an inter-disciplinary research field that involves photonic devices, integrated circuits design, packaging, photonic device modeling, electronic-photonic co-simulation, applications, and standardization. This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform, identify the key challenges, and point out the potential solutions, hoping to encourage collaboration between different research fields to accelerate the development of CPO technology. Graphical Abstract

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“…The cavities consist of 650nm×285nm (width×thickness) InP-based wires embedding four InGaAsP strained quantum wells, drilled with a row of equally-sized holes (radius=123nm). The distance between the holes is varied according to [39] in order to obtain a Gaussian field profile for the resonant mode which enables Q factors higher than 10 4 (10 6 in simulations) with V~(λ/n) 3 . The thickness of the BCB layer is 260nm.…”

Section: Fabrication Of the Hybrid Phc-based Nanocavity Lasermentioning

confidence: 99%