High aspect ratio silicon etch: A review

Abstract

High aspect ratio (HAR) silicon etch is reviewed, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies. Chronologically, HAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, single-step etch at cryogenic conditions in inductively coupled plasma (ICP) combined with RIE, time-multiplexed deep silicon etch in ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near room temperature. Key specifications are HAR, high etch rate, good trench sidewall profile with smooth surface, low aspect ratio dependent etch, and low etch loading effects. Till now, time-multiplexed etch process is a popular industrial practice but the intrinsic scalloped profile of a time-multiplexed etch process, resulting from alternating between passivation and etch, poses a challenge. Previously, HAR silicon etch was an application associated primarily with microelectromechanical systems. In recent years, through-silicon-via (TSV) etch applications for three-dimensional integrated circuit stacking technology has spurred research and development of this enabling technology. This potential large scale application requires HAR etch with high and stable throughput, controllable profile and surface properties, and low costs.

High-uniformity centimeter-wide Si etching method for MEMS devices with large opening elements

“…The second is global loading effect, which is related to pattern density, i.e., the area of exposed silicon. 18,20) It causes nonuniformity in etching rate on a large scale. In such largearea etching, the ratio of the resist-protected area to the notprotected area is extremely different.…”

Use of Hard Mask for Finer (<10 μm) Through Silicon Vias (TSVs) Etching

“…5(a). Etch rate uniformity deteriorates when pressure or average loading increase [10], and Argon does not chemically reacted with the poly and removes the passivation layer by sputtering the polymer with high energetic ions [11].…”

Thermal Microactuators

“…DRIE silicon etching is commonly referred to as Bosch etching and was patented by Lärmer and Schlip (1992). A thorough review of DRIE high aspect ratio silicon etching is presented by Wu et al (2010). In SOI MEMS fabrication, the initial wafer has three layers: a single crystal silicon substrate wafer, a thin thermally grown silicon dioxide layer referred to as the buried oxide, and a mechanically thinned single crystal silicon layer called the device layer.…”