Heterogeneous Integration of III–V Materials by Direct Wafer Bonding for High-Performance Electronics and Optoelectronics

Caimi, Daniele; Tiwari, Preksha; Sousa, Marilyne; Moselund, Kirsten E.; Zota, Cezar B.

doi:10.1109/ted.2021.3067273

Cited by 24 publications

(16 citation statements)

References 99 publications

(88 reference statements)

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“…Then, the material is bonded onto a Si wafer with a 2 μm thick SiO 2 layer in between, serving as an optical insulator layer, and the donor wafer material is removed. More information on direct wafer-bonding techniques can be found in ref ( 42 ). For the microdisk cavities, the antennae are first defined by a lift-off process using a PMMA bilayer as a resist and 40 nm electron-beam evaporated Au and a 2 nm Ti adhesion layer.…”

Section: Resultsmentioning

confidence: 99%

Single-Mode Emission in InP Microdisks on Si Using Au Antenna

et al. 2022

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An important building block for on-chip photonic applications is a scaled emitter. Whispering gallery mode cavities based on III–Vs on Si allow for small device footprints and lasing with low thresholds. However, multimodal emission and wavelength stability over a wider range of temperature can be challenging. Here, we explore the use of Au nanorod antennae on InP whispering gallery mode lasers on Si for single-mode emission. We show that by proper choice of the antenna size and positioning, we can suppress the side modes of a cavity and achieve single-mode emission over a wide excitation range. We establish emission trends by varying the size of the antenna and show that the far-field radiation pattern differs significantly for devices with and without antenna. Furthermore, the antenna-induced single-mode emission is dominant from room temperature (300 K) down to 200 K, whereas the cavity without an antenna is multimodal and its dominant emission wavelength is highly temperature-dependent.

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Section: Resultsmentioning

confidence: 99%

Single-Mode Emission in InP Microdisks on Si Using Au Antenna

et al. 2022

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“…Monolithic 3D Integration of III−V-Based RF Devices on Si CMOS Circuits. There are three main requirements to achieve monolithic 3D integration of III−V-based RF devices on Si CMOS circuits for RF systems (Figure 1a): (1) high quality of stacked III−V layers (quality degradation such as reduced carrier mobility directly affects RF performance 23 );…”

Section: Resultsmentioning

confidence: 99%

“…There are three main requirements to achieve monolithic 3D integration of III–V-based RF devices on Si CMOS circuits for RF systems (Figure a): (1) high quality of stacked III–V layers (quality degradation such as reduced carrier mobility directly affects RF performance); (2) low process temperatures for stacking III–V layers and fabricating top devices (temperatures of more than 400 °C can degrade bottom devices and interconnections); (3) optimized monolithic 3D structure (appropriate ILD thickness is required to maintain a short interconnection while minimizing the back parasitic capacitance of a top-tier RF device).…”

Section: Results and Discussionmentioning

confidence: 99%

“…Recently, many research groups have shown the feasibility of heterogeneous and monolithic 3D integration for RF systems by fabricating III–V-based RF devices on Si, − but most reported works have been done on a Si substrate rather than on Si CMOS circuits. More recently, III–V-based RF devices have been demonstrated on Si CMOS (transistor level), but the performance of III–V-based RF devices has been limited to lower than that on the Si substrate. We also demonstrated III–V-based RF devices on the Si substrate and Si CMOS in our previous work, , showing sufficient potential but still having limited RF performance and having not realized a full integration of RF/analog-digital mixed-signal circuits.…”

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Heterogeneous and Monolithic 3D Integration of III–V-Based Radio Frequency Devices on Si CMOS Circuits

Jeong

Kim

et al. 2022

ACS Nano

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Next-generation wireless communication such as sixth-generation (6G) and beyond is expected to require high-frequency, multifunctionality, and power-efficiency systems. A III−V compound semiconductor is a promising technology for high-frequency applications, and a Si complementary metal-oxide-semiconductor (CMOS) is the never-beaten technology for highly integrated digital circuits. To harness the advantages of these two technologies, monolithic integration of III−V and Si electronics is beneficial, so that there have been everlasting efforts to accomplish the monolithic integration. Considering that the on horizon 6G wireless communication requires faster and more energy-efficient system-on-chip technologies, it is imperative to realize a radio frequency (RF) system in which III−V technology and Si CMOS technology are integrated at a device level.Here we report heterogeneous and monolithic three-dimensional (3D) analog/ RF-digital mixed-signal integrated circuits that contain two types of InGaAs high-electron-mobility transistors (HEMTs) designed for high f T and f MAX in the top and Si CMOS mixed-signal circuits consisting of an analog-to-digital converter and digital-to-analog converter in the bottom. A high unity current gain cutoff frequency of 448 GHz and unity power gain cutoff frequency of 742 GHz have been achieved by the f T oriented and f MAX oriented InGaAs HEMTs, respectively, without being affected by mixed-signal interference. At the same time, the bottom Si CMOS circuits provide valid signals without any performance degradation by the integration process.

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“…Another potential integration method to combine GaN and silicon CMOS is wafer bonding [18], [19]. For the Direct Wafer Bonding, DWB, a demanding Chemical Mechanical Polishing, CMP, step is necessary to achieve the required planar surface with sub-1 nm surface topology [20], [21], [22].…”

Section: Direct Wafer Bondingmentioning

confidence: 99%

Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing

Lerner¹,

Hansen²

2021

ISPS'21 Proceedings

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Several approaches for close integration of power switches with CMOS logic are subject of technical evaluations and academic discussions. This paper identifies the commercially relevant processing steps of different integration methods (HV and SOI CMOS, monolithic integration in SOI and in GaN, Direct Wafer Bonding, micro-Transfer-Printing of GaN on CMOS and CMOS on GaN) and compares them on simple cost per wafer and cost per chip models. Four examples of real ICs verify the simple costs per chip model. Commercially attractive high voltage to logic partitionings are identified for the different integration approaches.

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Heterogeneous Integration of III–V Materials by Direct Wafer Bonding for High-Performance Electronics and Optoelectronics

Cited by 24 publications

References 99 publications

Single-Mode Emission in InP Microdisks on Si Using Au Antenna

Single-Mode Emission in InP Microdisks on Si Using Au Antenna

Heterogeneous and Monolithic 3D Integration of III–V-Based Radio Frequency Devices on Si CMOS Circuits

Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing

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