Heterogeneous and Monolithic 3D Integration of III–V-Based Radio Frequency Devices on Si CMOS Circuits

Abstract

Next-generation wireless communication such as sixth-generation (6G) and beyond is expected to require high-frequency, multifunctionality, and power-efficiency systems. A III−V compound semiconductor is a promising technology for high-frequency applications, and a Si complementary metal-oxide-semiconductor (CMOS) is the never-beaten technology for highly integrated digital circuits. To harness the advantages of these two technologies, monolithic integration of III−V and Si electronics is beneficial, so that there have been everlasting efforts to accomplish the monolithic integration. Considering that the on horizon 6G wireless communication requires faster and more energy-efficient system-on-chip technologies, it is imperative to realize a radio frequency (RF) system in which III−V technology and Si CMOS technology are integrated at a device level.Here we report heterogeneous and monolithic three-dimensional (3D) analog/ RF-digital mixed-signal integrated circuits that contain two types of InGaAs high-electron-mobility transistors (HEMTs) designed for high f T and f MAX in the top and Si CMOS mixed-signal circuits consisting of an analog-to-digital converter and digital-to-analog converter in the bottom. A high unity current gain cutoff frequency of 448 GHz and unity power gain cutoff frequency of 742 GHz have been achieved by the f T oriented and f MAX oriented InGaAs HEMTs, respectively, without being affected by mixed-signal interference. At the same time, the bottom Si CMOS circuits provide valid signals without any performance degradation by the integration process.

Depolarization induced III–V triatomic layers with tristable polarization states

“…Products based on III-V semiconductors have been widely employed in mobile devices, wireless networks, satellite communications, and optoelectronics. [18][19][20] For example, 4th-generation (4G) wireless networks depend on thin-film bulk acoustic resonators consisting of piezoelectric wurtzite AlN. At present, the industry of III-V semiconductor manufacturing is well established.…”

Heterogeneous and Monolithic 3D Integration Technology for Mixed-Signal ICs

“…As a result, heterogeneous and monolithic 3D (M3D) integration has been extensively studied in order to maximize the benefits of 3D integration in terms of low power consumption, interconnection delay, and via densities. M3D-based RF transistors on Si CMOS ICs, high-resolution microdisplays on Si CMOS driving circuits, and imaging systems on MOSFETs and neuromorphic devices have been demonstrated [10][11][12][13][14][15][16][17][18][19]. Furthermore, the aforementioned studies demonstrated the heterogeneous integration of different materials Furthermore, the aforementioned studies demonstrated the heterogeneous integration of different materials of III-V compound semiconductors with Si-and Ge-based bottom devices, indicating better flexibility in process design and performance improvements, as shown in Figure 1.…”

“…For future next-generation wireless communication, the co-integration of III-V-based RF devices and Si CMOS digital circuits is positively necessary, as shown in Figure 4a. We have successfully implemented the heterogeneous and monolithic 3D integration of III-V-based RF devices on Si CMOS by direct wafer bonding [10]. The cross-sectional SEM image is shown in Figure 4b.…”

Ferroelectric Hafnia-Based M3D FeTFTs Annealed at Extremely Low Temperatures and TCAM Cells for Computing-in-Memory Applications

“…Another possible way to implement high-density CIM devices is to use the monolithic three-dimensional (M3D) integration technique. Memory devices with M3D integration techniques exhibit excellent scalability and high-speed performance due to the possibility of integrating devices in the vertical direction. − Despite the advantage of M3D integration, few studies have been conducted due to the high process difficulty. Especially, when the M3D devices are fabricated, the wafer bonding process involves problems such as the wafer’s compound yield and wafer warpage .…”