Hardware Specification Generated from Estelle

Wytrębowicz, Jacek

doi:10.1007/978-0-387-34892-6_27

Cited by 5 publications

(6 citation statements)

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“…Several hardware implementation techniques for SDL and Estelle specifications have been proposed [3,6,14]. However, they require complicated operations for mutual exclusion in accessing shared resources among concurrent EFSMs since only one-to-one asynchronous communication between EFSMs is available in SDL and Estelle.…”

Section: Introductionmentioning

confidence: 99%

“…For the purpose, researchers have begun focusing on the use of formal specification languages (formal description techniques: FDT) for communication protocols as starting points to synthesize hardware circuits for protocols [6,9,11,14]. Using FDTs, message exchanges among concurrent processes such as multi-point/broadcast communication and mutual exclusion for accessing shared resources (e.g., FIFO queue) can be represented in a straightforward way.…”

Section: Introductionmentioning

confidence: 99%

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Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization

Katagiri

Yasumoto

Kitajima

et al. 2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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In this paper, we propose a technique to implement communication protocols as hardware circuits using a model of concurrent EFSMs with multi-way synchronization. Since use of multi-way synchronization enables simple and comprehensible specifications of recent communication protocols which frequently use complicated mechanisms such as mutual exclusion and dynamic job assignment, the proposed model is expected to reduce development cost in designing/developing such protocols. We implement specifications described in the model so that EFSMs work synchronously with the same clock, and that the synchronization mechanism for checking executability of each tuple of synchronizing transitions is implemented as a combinational logic circuit. Through some experiments, we have confirmed that the proposed technique can synthesize hardware circuits with relatively good performances for practical use.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization

Katagiri

Yasumoto

Kitajima

et al. 2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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“…To specify hardware circuits formally, the description techniques LOTOS [1,12], Estelle [15] and SDL [13] have been proposed. With these techniques, we can easily describe schemes for hardware circuits using predefined component libraries, and can verify/validate them.…”

Section: Introductionmentioning

confidence: 99%

Hardware Synthesis from Protocol Specifications in LOTOS

Yasumoto

Kitajima

Higashino

et al. 1998

IFIP Advances in Information and Communication Technology

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In this paper, we propose a technique for hardware implementation of protocol specifications in LarOS. For the purpose, we define a new model called synchronous EFSMs consisting of concurrent EFSMs and a finite set of multi-rendezvous indications among their subsets, and propose a conversion algorithm from a subset of LaroS. The derived synchronous EFSMs can be easily implemented as a synchronous sequential circuit where all the modules corresponding to the EFSMs work synchronously with the same clock. By applying our technique to the Abracadabra protocol, it is confirmed that the derived circuit handles multi-rendezvous efficiently.

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“…In general, these two environments are based on different description languages requiring an interface to translate one language into the other. Several efforts have been made to translate a system level specification into a Hardware Description Language (HDL) such as the work of Kloos (Kloos, 1993) ori the translation of Lotos into VHDL and those of Pirmez (Pirmez, 1995), and Wytrebowicz (Wytrebowicz, 1995), on the Estelle-VHDL mapping.…”

Section: Introductionmentioning

confidence: 99%