Hardware Synthesis from Protocol Specifications in LOTOS

Abstract

In this paper, we propose a technique for hardware implementation of protocol specifications in LarOS. For the purpose, we define a new model called synchronous EFSMs consisting of concurrent EFSMs and a finite set of multi-rendezvous indications among their subsets, and propose a conversion algorithm from a subset of LaroS. The derived synchronous EFSMs can be easily implemented as a synchronous sequential circuit where all the modules corresponding to the EFSMs work synchronously with the same clock. By applying our technique to the Abracadabra protocol, it is confirmed that the derived circuit handles multi-rendezvous efficiently.

Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization

“…A set of all rendezvous indications is said to be the rendezvous table and denoted by R. If several EFSMs with the parallel operators specified among them are given, the corresponding rendezvous table can be calculated automatically [15]. In this paper, due to space restriction, we omit the details of the calculation.…”

“…Using the above technique, the number of rendezvous indications is bound to Op k n [15] where p is the maximum number of combinations of the synchronizing EFSMs on a gate (usually p can be considered as a constant).…”

Specification and Verification of Synchronous Hardware using LOTOS

“…The European project FORMAT [5] studied the translation of LOTOS to VHDL. Other hardware applications of LOTOS have included bus protocols [3,23] and hardware synthesis [27].…”

Hardware Implementation of Concurrent Periodic EFSMs

“…[1,13] have proposed hardware implementation techniques using SDL and Estelle, respectively, and [8,10,14] have proposed techniques based on LOTOS [5]. However, those existing techniques do not handle timing constraints for event execution nor guarantee real-time processing of tasks in the generated circuits.…”

“…Here, we maximize the total sum of executable time ranges of I/O events. Based on the techniques we previously proposed in [7,14], a given specification in the proposed model is implemented as a hardware circuit where it consists of sequential circuits corresponding to EFSMs and a combinational logic circuit for the controller of multi-way synchronization among EFSMs. For timing guarantees, we construct a scheduling circuit indicating schedulable event sequences at each time.…”