Abstract:A methodology that efficiently translates Estelle formal specifications into a VHDL description, suitable for High Level Synthesis of communication protocols is proposed. The effect of the protocol description style in VHDL on the result of the HLS scheduling step is discussed by report to the Dynamic Loop Scheduling algorithm. An example using a test protocol is given.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.