Hardware compilation for FPGA-based configurable computing machines

Abstract

Configurable computing machines are an emerging class of hybrid architectures where a field programmable gate array (FPGA) component is tightly coupled to a general-purpose microprocessor core. In these architectures, the FPGA component complements the general-purpose microprocessor by enabling a developer to construct application-specific gate-level structures on-demand while retaining the flexibility and rapid reconfigurability of a fully programmable solution. High computational performance can be achieved on the FPGA component by creating custom data paths, operators, and interconnection pathways that are dedicated to a given problem, thus enabling similar structural optimization benefits as ASICs. In this paper, we present a new programming environment for the development of applications on this new class of configurable computing machines. This environment enables developers to develop hybrid hardware/software applications in a common integrated development framework. In particular, the focus of this paper is on the hardware compilation part of the problem starting from a software-like algorithmic process-based specification.

An end-to-end approach for the automatic derivation of application-aware error detectors

“…Conversion of C code into synthesizable VHDL has been extensively studied in literature [17] [3]. However, such techniques are generic and are thus inefficient in a specialized context.…”

Attacking the semantic gap between application programming languages and configurable hardware

“…Systems that extend a conventional language with non-standard parallel constructs (which means they cannot be compiled by a standard compiler for the base language) include Handel-C [18], HardwareC [20], RL [21], Transmogrifier C [13], Spyder C++ [14], Data Parallel C [8], Picasso [19] and SA-C [9]. Unconventional application languages created with an explicit parallel programming model include CAM [25], TAO [23] and an unnamed language by Wirth [7].…”

Design methodology for construction of asynchronous pipelines with Handel-C

“…The advent of Clanguage silicon compilers now offers a means of improving developer productivity and simplifying system design by replacing hardware-level descriptions with algorithm-level system specifications coded in the 'C' programming language [13,14]. Furthermore, given the availability of high-capacity, programmable hardware (for example the Virtex-II can incorporate up to four PowerPC cores), there is now both a need and an opportunity to incorporate software methods into hardware design and development.…”