Design methodology for construction of asynchronous pipelines with Handel-C

Self, R. P.; Fleury, Martin; Downton, A.C.

doi:10.1049/ip-sen:20030206

Cited by 5 publications

(3 citation statements)

References 17 publications

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“…Some C-based hardware definition methods [2,6,12,13,14,15] have instruments for pipelining, however here the developer has to prescribe this function by a specific instruction to which a special variable type can belong, or needs special preconditions, instruments or has to construct pipelines manually.…”

Section: Pipeliningmentioning

confidence: 99%

Pipeline mode in C-based direct hardware implementation

Arató¹,

Csák²

2008

Per. Pol. Elec. Eng.

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In this paper a methodology is presented that enables the pipeline function of hardware blocks created by C-based direct hardware design. The method is embedded into the C-based design methodology worked out by the authors earlier. This pipeline enabling method is rather flexible, needs no special efforts. With the help of a simple state-machine-based entity, blocks of different execution times can build up the pipeline, even with data-dependent duration. A data-spreading technique solves data consistency. Pipeline sectioning -chosing the right and balanced granularity versus pipelining overhead -is an optimisation matter. Simulation results prove the correctness of the method.Keywords C-based design · reuse · component based design · parallel processing · pipelining · hardware-software codesign

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Section: Pipeliningmentioning

confidence: 99%

Pipeline mode in C-based direct hardware implementation

Arató¹,

Csák²

2008

Per. Pol. Elec. Eng.

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“…Application code development for the FPGA may be through Celoxica's 4 Handel-C language [5], which allows hardware compiled programs to be written in a C-like language. Host-to-platform communication is through Celoxica's Data Streaming Manager (DSM), which is activated through a Handel-C Application Programming Interface (API).…”

Section: Introductionmentioning

confidence: 99%

High-level Design Environments for FPGA-based Content Processing

Cheng

Fleury

2008

2008 IEEE/ASME International Conference on Mechtronic and Embedded Systems and Applications

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Abstract-Content processing of network packets requires real-time rates and high throughput, which a platform Field Programmable Gate Array (FPGA) can provide. It also requires a high-level design approach that allows time-to-market deadlines to be met. The paper introduces a two-step development process that allows the enhanced memory and I/O facilities of a Content Processor to be utilized but also avail of the more complete simulation and debug facilities on a compatible development board. This can be achieved by providing a complimentary or shadow design environment. High-level design is available for FPGAs in terms of hardware compilation and the provision of an on-chip runtime environment (RTE). The Tarari Content Processor supports both of these but investigation has shown that the RC200 development board assists in reducing design turn-around time.

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“…Communicating Hardware Processes [78]. Asynchronous synthesis systems that rely on syntax-directed translation but are based on languages that are not related to CSP, such as C [68] and VHDL [71], have also been reported.…”

Section: Literature Reviewmentioning

confidence: 99%

Design methodologies for low-power asynchronous-logic digital systems

Law¹

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Asynchronous design has been an active area of research since the 1950s, but has hitherto yet to achieve widespread use or acceptance. This is largely because several major problems continue to persist that inhibit its acceptance in the very large-scale integration industry as a viable alternative to the prevalent synchronous design. This thesis addresses one such problem: how to reduce the circuit area and power dissipation of asynchronous control networks. Three main contributions are made in this thesis to the design of asynchronous pipelines with low asynchronous control overheads. First, a synthesis method for asynchronous pipelines is proposed that adopts a coarse-grain approach to the synthesis of asynchronous control networks, thereby leading to low asynchronous control overhead pipelines. It also has the advantages of offering a largely transparent modeling style for asynchronous communication and ease for integration into the conventional synchronous design flow. The efficacy of the proposed synthesis method is demonstrated through the design of a Reed-Solomon error detector and an interpolated finite-impulse-response filterbank-the simulated circuit implementations based on the proposed synthesis method dissipate on the average 31% less energy than those implemented by comparable reported synthesis methods. Second, two optimization methods are proposed for reducing the circuit area and power dissipation of asynchronous control networks while satisfying pipeline throughput constraints. The first proposed optimization method-handshake component fusion-is a form of peephole optimization that iteratively selects a pair of handshake components that share input channel sources or output channel destinations and replaces them with a single component. The second proposed optimization method-optimal decoupling-searches for the optimal mix of handshake components of different degree of concurrency in a given asynchronous control network with the objective of incurring the least circuit area and power dissipation for the control network, while satisfying a throughput constraint. The proposed optimization methods are applied on three designs and are found to reduce the asynchronous control networks' transistor count and energy dissipation by, on the average, 28% and 36%, respectively. A fundamental requirement of the proposed optimization methods is that the minimal-support S-invariants for the Petri net models of the asynchronous control networks are recomputed at each optimization iteration. vii ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library Arising from the fundamental requirement mentioned above, the third main contribution of the thesis is a fast and memory-efficient algorithm for computing all minimal-support S-invariants for ordinary Petri nets. Based on a large number of test problems, the proposed algorithm is demonstrated to be at least 2.2x faster and 1.8x more memory efficient than reported algorithms. The proposed synthesis method, ...

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Design methodology for construction of asynchronous pipelines with Handel-C

Cited by 5 publications

References 17 publications

Pipeline mode in C-based direct hardware implementation

Pipeline mode in C-based direct hardware implementation

High-level Design Environments for FPGA-based Content Processing

Design methodologies for low-power asynchronous-logic digital systems

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