An end-to-end approach for the automatic derivation of application-aware error detectors

Abstract

Critical Variable Recomputation (CVR) based error detection provides high coverage for data critical to an application while reducing the performance overhead associated with detecting benign errors. However, when implemented exclusively in software, the performance penalty associated with CVR based detection is unsuitably high. This paper addresses this limitation by providing a hybrid hardware/software tool chain which allows for the design of efficient error detectors while minimizing additional hardware. Detection mechanisms are automatically derived during compilation and mapped onto hardware where they are executed in parallel with the original task at runtime. When tested using an FPGA platform, results show that our approach incurs an area overhead of 53% while increasing execution time by 27% on average.

Hardware/software optimization of error detection implementation for real-time embedded systems

“…In this case, the path tracking alone incurs a time overhead of up to 400%, while the overhead due to variable checking is up to 80% [15]. Complete hardware implementations of path tracking and expression checking are proposed in [15] and [14]. In fact, between the extreme solutions of implementing all error detection in software, on the one side, and performing it in hardware, on the other side, there is a wide range of possible alternatives characterized by the particular implementation decision taken for each process in the application.…”

“…As a result, customized solutions are created, tuned to better suit each application's needs. As shown in [15] and [14] the main idea of this application-aware technique is to identify, based on specific metrics [16], critical variables in a program. A critical variable is defined as "a program variable that exhibits high sensitivity to random data errors in the application" [15].…”

“…The initial applications, available as C code, are represented as a set of process graphs. The code is processed through the error detection instrumentation framework [14]. This framework outputs the initial application code with the embedded error detectors, as well as the VHDL code needed to synthesize error detector modules on FPGA.…”

Towards fault-tolerant embedded systems with imperfect fault detection

“…On the other hand, even if implementable, perfect detectors typically come with high resource and timing overheads. In recent work [12,18] it has been shown that the time needed for high-coverage fault detection may become much longer than the execution time of the task itself (e.g. the timing overhead could be 400% using techniques proposed in [12]).…”

“…In recent work [12,18] it has been shown that the time needed for high-coverage fault detection may become much longer than the execution time of the task itself (e.g. the timing overhead could be 400% using techniques proposed in [12]). Hence, approaches under this assumption are very pessimistic, as the most expensive fault detector is selected for every task.…”