Hardware/software optimization of error detection implementation for real-time embedded systems

Lifa, Adrian; Eles, Petru; Peng, Zebo; Izosimov, Viacheslav

doi:10.1145/1878961.1878970

Cited by 14 publications

(11 citation statements)

References 22 publications

(40 reference statements)

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“…We address the problem from two angles: inter-task and intra-task optimization. In the first case, we propose hardware/software codesign techniques that leverage the advantages of partial dynamic reconfiguration of FPGAs in order to minimize the global worst-case schedule length of an application, while meeting the imposed hardware cost constraints and tolerating multiple transient faults [LEPI10]. In the latter case, we propose a technique to minimize the average execution time of a program by speculatively prefetching on the FPGA those error detection components that will provide the highest performance improvement [LEP11].…”

Section: Summary Of Contributionsmentioning

confidence: 99%

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

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M odern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as flexibility, energyefficiency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconfiguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures.In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on reconfigurable and heterogeneous platforms. We focus on performance enhancement for dynamically reconfigurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems.The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have confirmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems. v vi Populärvetenskaplig Sammanfattning I dag är inbyggda system vanligt förekommande och deras antal fortsätter att öka. De används inom en mängd olika domäner, t.ex. hemelektronik, fordonsindustri, flygelektronik, medicin, etc., och de hittas nästan överallt omkring oss: från våra telefoner, bärbara datorer och tvättmaskiner till våra bilar. De applikationer som körs på dessa system har flera olika ökande krav: högprestanda, energieffektivitet, flexibilitet, feltolerans, realtidsegenskaper, och naturligtvis låg kostnad. För att kunna uppfylla dessa krav har industrin anammat arkitekturer som är mer och mer heterogena och som har omkonfigureringsmöjligheter. Olyckligtvis ökar detta komplexiteten när man ska utforma effektiva inbyggda system. I detta sammanhang blir det av yttersta betydelse att utveckla effektiva optimeringsmetoder och verktyg.Dagens applikationer består av en blandning av mjukvarukomponenter som har mycket olika energi-och prestandaegenskaper beroende på vilka hårdvaruenheter där de körs på, vilket gör dem lämpliga för heterogena plattformar. En heterogen plattform består av olika typer av hårdvaruen-heter, var och en med sina egenskaper, som riktar sig till vissa tillämpn-ingsområden. Under det senaste decenniet har utvecklingen av rekonfigurerbara hårdvarutekniker accelererat, vilket bidrar till den ökande populariteten för fältprogrammerbara grindmatriser (FPGA). Idag, ger hård-varutillverkare stöd för partiell dynamisk omkonfigurering; detta innebär att delar av en FPGA kan konfigureras vid run-time, medan andra delar förblir fullt fungerande. Dessa tekniska framsteg har...

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Section: Summary Of Contributionsmentioning

confidence: 99%

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

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“…In [26], the authors consider another important tradeoff, namely the tradeoff between hardware-implemented and software-implemented fault detection. They propose to selectively implement fault detectors in a FPGA fabric tightly coupled with the processor, so that the fault detector can run in parallel with the original program and the timing overhead of fault detection can be reduced.…”

Section: Related Workmentioning

confidence: 99%

“…FPGA-accelerated fault detection is currently not considered in our work. To take this issue into account, the problems considered in [26] and [17] have to be combined. Here, the design goal is to decide both which fault detector to implement and where to implement.…”

Section: Related Workmentioning

confidence: 99%

A framework for reliability-aware design exploration on MPSoC based systems

Huang

Raabe

Huang³

et al. 2012

Des Autom Embed Syst

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Applying system-level fault-tolerant techniques such as active redundancy is a promising way to enhance the system reliability for safety-related applications. Embedded system design using active redundancy is a challenging task that involves solving two major problems, namely finding the optimal redundancy configuration and mapping/scheduling of the application (including the redundant components) to the platform under timing and reliability constraints. This paper presents a framework for automatic synthesis of fault-tolerant designs on multiprocessor platforms. The core of the framework consists of: (1) a reliability analysis, that computes the system-level reliability in the presence spatial and temporal redundancy, and (2) an optimization approach for reliability-aware design space exploration. The proposed approach considers both transient and permanent faults and is among the first to support system design using imperfect fault detectors. The framework takes an application model, a platform model and a set of application requirements as input, and generates the recommended design parameters, including task-to-processor binding, task schedule and the selection/placement of redundancy. The effectiveness of our approach is illustrated using several case studies.

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“…Perfect fail-silent behavior is one assumption that is often used in literature. It is assumed that all faults are detected within a certain time interval and the fault-detection overhead is contained in the tasks' WorstCase Execution Times (WCETs), e.g., in fault-tolerant task scheduling [8,15,4,17,6,5], in reliability-aware energy management [16,20,22] and in error-aware system design [9,10]. With this assumption, each task will produce either a correct output or no output at all.…”

Section: Introductionmentioning

confidence: 99%

Towards fault-tolerant embedded systems with imperfect fault detection

Huang

Raabe

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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Many state-of-the-art approaches on fault-tolerant system design make the simplifying assumption that all faults are detected within a certain time interval. However, based on a detailed experimental analysis, we observe that perfect fault detection is not only an impractical assumption but even if implementable also a suboptimal design decision. This paper presents an approach that takes imperfect fault detection into account. Novel analysis and optimization techniques are developed, which distinguish detectable and undetectable faults in the overall workflow. Besides synthesizing the task schedules, our approach also decides which of the available fault detectors is selected for each task instance. Experimental results show that our approach finds solutions with several orders of magnitude higher reliability than current approaches.

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Hardware/software optimization of error detection implementation for real-time embedded systems

Cited by 14 publications

References 22 publications

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

A framework for reliability-aware design exploration on MPSoC based systems

Towards fault-tolerant embedded systems with imperfect fault detection

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