Attacking the semantic gap between application programming languages and configurable hardware

Snider, Greg; Shackleford, Barry; Carter, Richard J.

doi:10.1145/360276.360322

Cited by 27 publications

(18 citation statements)

References 31 publications

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“…One of the main reasons for this is poor support for concurrency in general-purpose programming languages. This so-called semantic gap [SSC01] focused efforts on extending conventional programming languages with low-level constructs leading to the emergence of languages that are closer to metal.…”

Section: Hardware Compilation Via Geometry Of Synthesismentioning

confidence: 99%

On the Compositionality of Round Abstraction

Ghica

Menaa

2010

CONCUR 2010 - Concurrency Theory

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Game Semantics is an approach to denotational semantics that has been successful in providing accurate, fully abstract models for various programming languages. It has thereafter been applied, amongst other things, to model checking, access control analysis, information flow analysis, and recently, hardware synthesis.While the roots of modern Game Semantics are sequential, several game models of asynchronous concurrency have since been devised. However, synchronous concurrency has not been considered hitherto.This thesis studies synchronous concurrency in game-like models. The central idea is to investigate deriving such synchronous models from their asynchronous counterparts using round abstraction-a technique that allows aggregating a sequence of computational steps to form a larger, more abstract macro-step.We define round abstraction within a trace-semantic setting that generalises game semantic models. We note that, in general, round abstraction is not compositional. We then identify sufficient conditions to guarantee correct composition, thereby proposing a framework for round abstraction that is sound when applied to synchronous and asynchronous behaviours.

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Section: Hardware Compilation Via Geometry Of Synthesismentioning

confidence: 99%

On the Compositionality of Round Abstraction

Ghica

Menaa

2010

CONCUR 2010 - Concurrency Theory

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“…al. [9]. The PACT project [10] at Northwestern University performs C to hardware synthesis by taking power/performance trade off into account.…”

Section: Related Workmentioning

confidence: 99%

A Model for Hardware Realization of Kernel Loops

Liao

Wong

Mitra

2003

Field Programmable Logic and Application

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Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In this paper, we consider two important loop optimization techniques, namely loop unrolling and software pipelining that can impact the performance and cost of the synthesized hardware. We propose a novel model that accounts for various characteristics of a loop, including dependencies, parallelism and resource requirement, as well as certain high level constraints of the implementation platform. Using this model, we are able to deduce the optimal unroll factor and technique for achieving the best performance given a fixed resource budget. The model was verified using a compiler-based FPGA synthesis framework on a number of kernel loops. We believe that our model is general and applicable to other synthesis frameworks, and will help reduce the time for design space exploration.

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“…The advent of Clanguage silicon compilers now offers a means of improving developer productivity and simplifying system design by replacing hardware-level descriptions with algorithm-level system specifications coded in the 'C' programming language [13,14]. Furthermore, given the availability of high-capacity, programmable hardware (for example the Virtex-II can incorporate up to four PowerPC cores), there is now both a need and an opportunity to incorporate software methods into hardware design and development.…”

Section: Introductionmentioning

confidence: 99%

Design methodology for construction of asynchronous pipelines with Handel-C

2003

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CSP channels are proposed as a means of developing high-level, asynchronous pipeline architectures over and above existing synchronous logic. Channel-based design allows hardware systems to be designed and constructed using top-down software engineering methods, which have not previously been available within hardware-software co-design. The intention is to enhance support for future large-scale co-designs. The design methodology and its performance implications are demonstrated through an exemplar, pipelined design of the Karhunen-Loève Transform (KLT) algorithm, implemented using the Handel-C silicon compiler applied to dense FPGAs.2

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Attacking the semantic gap between application programming languages and configurable hardware

Cited by 27 publications

References 31 publications

On the Compositionality of Round Abstraction

On the Compositionality of Round Abstraction

A Model for Hardware Realization of Kernel Loops

Design methodology for construction of asynchronous pipelines with Handel-C

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