Handshake protocols for de-synchronization

Blunno, I.; Cortadella, Jordi; Kondratyev, A.; Lavagno, Luciano; Lwin, Kelvin; Sotiriou, Christos

doi:10.1109/async.2004.1299296

Cited by 60 publications

(47 citation statements)

References 22 publications

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“…Several approaches have been proposed for translating synchronous circuits into asynchronous ones [4,3,12,14,11,5]. Our toolflow is similar to these, but the main thrust of our approach is different: we provide relative-timing optimization algorithms to reduce the area overheads typically introduced by such toolflows.…”

Section: Related Workmentioning

confidence: 99%

“…A promising way to address the lack of CAD tools for asynchronous design is to re-use existing synchronous tools, and translate their results into asynchronous circuits. Several papers explore this approach ( [4,3,12,14,11]): synchronous circuits are translated into quasi delay-insensitive (QDI) circuits. QDI circuits are synthesized assuming that gates and wires have fixed, but unbounded, delays.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

Chelcea

Venkataramani

Goldstein

2007

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)

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Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous toolflows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algorithms, based on timing interval analysis, for improving existing asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal algorithm and 1.8 times smaller for a heuristic one than the existing solutions. The optimized circuits are also shown to be resilient to large parametric variations, yielding better average-case latencies than their synchronous counterparts.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

Chelcea

Venkataramani

Goldstein

2007

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)

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“…Reference [11] suggests that desynchronisation results in circuits with almost identical area, performance and power consumption as the original synchronous ones. Desynchronised circuits, however, have smaller EMI due to the out-ofphase clocks, and better modularity due to the explicit handshakes encapsulating timing constraints.…”

Section: Desynchronisationmentioning

confidence: 99%

“…Desynchronisation [11] builds on these theoretical foundations in order to provide the designer with the option to derive a medium-grained asynchronous implementation from a traditional synchronous specification. Assuming an initial design implemented with edge-triggered flip-flops, it requires the following steps:…”

Section: Desynchronisationmentioning

confidence: 99%

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

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“…We used the 4-phase controller proposed in [18] for this comparison. That controller is shown in Fig.…”

Section: -Phase Controllermentioning

confidence: 99%

Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol

Mannakkara

Yoneda

2010

IEICE Trans. Inf. & Syst.

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SUMMARYA new pipeline controller based on the Early Acknowledgement (EA) protocol is proposed for bundled-data asynchronous circuits. The EA protocol indicates acknowledgement by the falling edge of the acknowledgement signal in contrast to the 4-phase protocol, which indicates it on the rising edge. Thus, it can hide the overhead caused by the resetting period of the handshake cycle. Since we have designed our controller assuming several timing constraints, we first analyze the timing constraints under which our controller correctly works and then discuss their appropriateness. The performance of the controller is compared both analytically and experimentally with those of two other pipeline controllers, namely, a very high-speed 2-phase controller and an ordinary 4-phase controller. Our controller performs better than a 4-phase controller when pipeline has processing elements. We have obtained interesting results in the case of a non-linear pipeline with a Conditional Branch (CB) operation. Our controller has slightly better performance even compared to 2-phase controller in the case of a pipeline with processing elements. Its superiority lies in the EA protocol, which employs return-to-zero control signals like the 4-phase protocol. Hence, our controller for CB operation is simple in construction just like the 4-phase controller. A 2-phase controller for the same operation needs to have a slightly complicated mechanism to handle the 2-phase operation because of the non-return-to-zero control signals, and this results in a performance overhead.

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Handshake protocols for de-synchronization

Cited by 60 publications

References 22 publications

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

Asynchronous on-chip networks

Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol

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