Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol

Abstract

SUMMARYA new pipeline controller based on the Early Acknowledgement (EA) protocol is proposed for bundled-data asynchronous circuits. The EA protocol indicates acknowledgement by the falling edge of the acknowledgement signal in contrast to the 4-phase protocol, which indicates it on the rising edge. Thus, it can hide the overhead caused by the resetting period of the handshake cycle. Since we have designed our controller assuming several timing constraints, we first analyze the timing constraints under which our controller correctly works and then discuss their appropriateness. The performance of the controller is compared both analytically and experimentally with those of two other pipeline controllers, namely, a very high-speed 2-phase controller and an ordinary 4-phase controller. Our controller performs better than a 4-phase controller when pipeline has processing elements. We have obtained interesting results in the case of a non-linear pipeline with a Conditional Branch (CB) operation. Our controller has slightly better performance even compared to 2-phase controller in the case of a pipeline with processing elements. Its superiority lies in the EA protocol, which employs return-to-zero control signals like the 4-phase protocol. Hence, our controller for CB operation is simple in construction just like the 4-phase controller. A 2-phase controller for the same operation needs to have a slightly complicated mechanism to handle the 2-phase operation because of the non-return-to-zero control signals, and this results in a performance overhead.

EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline

“…As for the latter circuit configurations, the configurations are divided into two groups according to whether a so-called Muller's C element which changes its output when all of its inputs coincide [6] is used or not. Among the variations in which Muller's C element is used, the two configurations proposed by Mannakkara et al [10] and Takizawa et al [11] are respectively superior because of their latently high throughput. The configuration of Ref.…”

“…The configuration of Ref. [10] confines three of four signal transitions in a handshake to a net data processing time by introducing the asymmetric delay module to accelerate the propagation of the acknowledge signal; however, no configurations for the circular pipelines have been revealed. The configuration of Ref.…”

“…For inequalities (3), ( 5), ( 7), ( 9), (10), and ( 11), the number of delay elements in Ds is increased when a timing violation occurs. When inequality ( 4) is violated, one or more delay elements are inserted immediately before the five-input NOR on the path of T 4(i−1) .…”

DCP: Improving the Throughput of Asynchronous Pipeline by Dual Control Path

“…Although the area of the DCP is doubled, it is still a tiny overhead because the control path takes rather a small rate in the area of the whole pipeline as shown in Table II. V. RELATED WORKS Handshake controller is the foundation of asynchronous circuits. Up to now, lots of handshake controllers have been designed [3], [4], [6], [7]. Furber and Day proposed SFLC, SdFLC and FdFLC [3].…”