Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders

Sravani, K. Girija; Rao, Rathnamala

doi:10.1002/cta.2771

Cited by 6 publications

(7 citation statements)

References 15 publications

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“…FIR filters have been used in many applications such as image processing processors, 3 CNNs, 19 filter banks, 20,21 and equalizers. 22 . Therefore, to evaluate the proposed designs, both 5-tap and 16-tap FIR filter with DA structure (MUX-Add-LUT) has been implemented in 65-nm technology.…”

Section: Simulation Resultsmentioning

confidence: 99%

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A power–performance partitioning approach for low‐power DA‐based FIR filter design with emphasis on datapath and controller

Ghamkhari

Ghaznavi‐Ghoushchi

2021

Circuit Theory & Apps

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Distributed arithmetic (DA) is an efficient way to implement sum-of-product units, which can be used in applications such as FIR filters, filter banks, image processing, and convolutional neural networks in IoT hardware accelerators. In this paper, a low-power architecture is offered centered on two key steps, coarse-grain power-performance partitioning and fine-grain separated power supply, and tuned a level shifter in any digital systems implemented based on RTL design. To examine the new design approach, two methods are proposed, at first exploring the power consumption and critical delay path and then separating the power supply of datapath and controller in DA with/without utilizing an implicit level shifter. To investigate power consumption and timing parameters, two 5-tap and 16-tap FIR-filters are implemented in 65-nm CMOS standard technology. In proposed1, dynamic and static power consumption of 16-tap (5-tap) FIR-filter is improved by 30% (15%) and 59% (59%), respectively.Nevertheless, the delay and slope of the generated signal in the shiftreg are significantly increased by reducing the power supply. To tackle this issue, the second method suggested with 26% (14%) improvement in dynamic power and 55% (58%) in static power consumption, which does not increase any delay in the output of shiftreg compared to conventional DA-based FIR filter with solitary power supply.distributed arithmetic, FIR filter, inner product, low-power, power-performance partitioning, RTL design and literature reviewInner product computation is an essential operation in digital signal processing (DSP) applications targeting image, audio, and video processing, as well as various applications of machine learning. 1 It could be used through a common multiply-accumulate (MAC) structure or an improved MAC method called distributed arithmetic (DA) to implement the sum of multiplications. The MAC structure is a high-consumption unit in implementation and not cost-effective in designing high-performance systems due to a large number of multipliers. DA structure is a bit-level rearrangement of

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Section: Simulation Resultsmentioning

confidence: 99%

“…Furthermore, corner (PVT) analysis is provided to ensure the acceptable performance of the proposed system against possible mismatches. FIR filters have been used in many applications such as image processing processors, 3 CNNs, 19 filter banks, 20,21 and equalizers 22 …”

Section: Simulation Resultsmentioning

confidence: 99%

A power–performance partitioning approach for low‐power DA‐based FIR filter design with emphasis on datapath and controller

Ghamkhari

Ghaznavi‐Ghoushchi

2021

Circuit Theory & Apps

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“…The state‐space equations of the orthogonal systems have to satisfy the following relationship:

{boldS}^{T} S = I

where

S = [\begin{matrix} left \\ left A & left B \\ left C & left D \end{matrix}]

and I denote the state‐space and unit matrices, respectively. Orthogonal systems require a lot of preliminary calculations, but offer fast implementation when Givens rotators in pipelined structures are used to implement FIR filters [16, 19–21]. The Givens rotator is described by the following equation:

[\begin{matrix} left \\ left u_{1} \\ left u_{2} \end{matrix}] = R [\begin{matrix} left \\ left y_{1} \\ left y_{2} \end{matrix}] = [\begin{matrix} left \\ left \cos (α) & left - \sin (α) \\ left \sin (α) & left \cos (α) \end{matrix}] [\begin{matrix} left \\ left y_{1} \\ left y_{2} \end{matrix}]

where u 1 , and u 2 denote the rotator inputs, y 1 , and y 2 denote the rotation outputs, α denotes the rotation angle, and

([], \begin{array}{l} left & \cos (α) & - \sin (α) \\ left & \sin (α) & \cos (α) \end{array})

denotes the rotation matrix.…”

Section: Introduction To Orthogonalitymentioning

confidence: 99%

“…The algorithms for the synthesis and implementation of the 1-D, 2-D and 3-D FIR filters [20,21] composed of Givens rotation structures are presented in Ref. [24,25].…”

Section: Introduction To Orthogonalitymentioning

confidence: 99%

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Synthesis algorithm of low sensitivity non‐separableN‐D finite impulse response filters configured of fast orthogonal 1‐D rotation structures implemented in field programmable gate arrays IC

Poczekajło

Wawryn

2022

IET Signal Processing

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In the article, a low sensitivity synthesis algorithm of a non-separable N-dimensional (N-D) finite impulse response filter implemented in Field Programmable Gate Arrays (FPGA) is proposed. The synthesis and implementation algorithms determine a pipelined non-separable N-D finite impulse response filter structure consisting of fast Givens rotator structures. The filter transfer function is expressed as a function of N independent 1-D orthogonal transfer functions in each of N directions to avoid difficult, multidimensional equation computation. The rotator structure is obtained using the COR-DIC algorithm. The proposed synthesis algorithm was used to design and optimise the structure of the Laplacian of Gaussian (LoG) 3-D filter. The obtained filter was implemented in FPGA IC and its parameters, sensitivity, processing time and signal-toquantisation noise ratio, were simulated and measured. The assessed results were compared with the theoretical analysis of the filter parameters. In order to verify the advantages of the proposed filtering solution, the parameter results were compared with the results of the convolution direct implementation and the orthogonal/non-orthogonal state-space implementation of the LoG 3-D filter.

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Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application

Senthilkumar¹,

Pandi

Sripriya

et al. 2023

Concurrency and Computation

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Summary Recustomize finite impulse response (RFIR) filter is designed to achieve lesser power consume, cost, area, and higher speed of system operation. This is used to remove the noises from the image and signal. Previously, several filters were designed for removing noises, but that filters consume more area, power, cost, and delay and did not provide accurate results and the error rate was increased. To overcome these issues, this work is proposed. In this work, the Recustomize finite impulse response (RFIR) filter is designed using truncation‐based scalable rounding approximate multiplier (TOSAM) and error reduced carry prediction approximate adder (ERCPAA) for image processing application. Here, TOSAM‐ERCPAA is used to speed up the filter design with less area and less power consumption. The proposed ERCPAA adder is divided into three blocks, such as carry prediction logic, approximate full adder cells array, constant truncation along error lessening logic, which can reduce the power and area. The proposed RFIR‐ TOSAM‐ERCPAA filter is designed and executed in Verilog programming language and the simulation is done in Xilinx ISE 14.5 design tools.

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Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders

Cited by 6 publications

References 15 publications

A power–performance partitioning approach for low‐power DA‐based FIR filter design with emphasis on datapath and controller

A power–performance partitioning approach for low‐power DA‐based FIR filter design with emphasis on datapath and controller

Synthesis algorithm of low sensitivity non‐separableN‐D finite impulse response filters configured of fast orthogonal 1‐D rotation structures implemented in field programmable gate arrays IC

Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application

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