H plasma cleaning and a-Si passivation of GaAs for surface channel device applications

Abstract

We discuss GaAs(001) cleaning and surface passivation for metal-oxide-semiconductor capacitors and field effect transistors fabricated with HfO2 as high-κ gate oxide. An amorphous-Si passivating layer is deposited by molecular beam deposition on a 2×1 reconstructed GaAs surface cleaned using a remote rf H plasma. The H plasma effectively removes C contaminants from the surface, but a progressive Ga enrichment and the presence of Ga–O bonds are observed. The capacitance-voltage measurements on capacitors under peripheral illumination show inversion, which is an indication of a passivated interface. The Dit distribution as function of energy in the band gap is extracted by using the conductance technique at high and low temperatures and is reported for HfO2/a-Si gate stacks on H-cleaned GaAs. The observed Dit distribution is asymmetric. Values as low as 7×1011 eV−1 cm−1 are found in the upper half of the band gap. One clear peak at 0.7 eV and a tail at 0.2 eV above the valence band maximum, which can be part of a second peak, are also observed. Transistor data confirm that a conducting channel is effectively opened at or very close to the GaAs surface.

GaAs on 200 mm Si wafers via thin temperature graded Ge buffers by molecular beam epitaxy

“…The slight reduction in the accumulation capacitance of sample GaAs400 at 1 MHz is attributed to the higher series resistance of the side contacts. In both samples the frequency dispersion is higher than in our previously published n-MOSCAPs on bulk GaAs substrates [17]. It has to be noted that after heteroepitaxy the gate stack was annealed at 350 1C only instead of 700 1C with the aim to keep the process compatible for Ge co-integration.…”

“…As a trial of a common gate stack for the Ge and GaAs areas, a 1.5 nm-thin amorphous Si (a-Si) passivating layer and 7 nm HfO 2 high-k gate dielectric were deposited. Details on the hydrogen plasma cleaning, a-Si passivating layer and HfO 2 high-k gate dielectric can be found elsewhere [17]. From the finished heterostructure MOSCAPs were fabricated with Pt gates and AuGe-Ni side-contacts.…”

Electrical Properties of HfTiON Gate-Dielectric GaAs Metal-Oxide-Semiconductor Capacitor With AlON as Interlayer

“…In Fig. 6, a Ga-O peak can be observed for the HfTiON/AlON and HfTiON samples, and the content of Ga-O bond at the interface is calculated to be 13.8% and 17.4%, respectively, based on the Ga-O/Ga3d peakarea ratio [14]. Obviously, the content of Ga-O bond is lower for the former than the latter, implying that the formation of Ga oxide at the interface is effectively suppressed by the AlON passivation layer.…”

“…However, compared with the SiO 2 /Si system, lack of a high-quality stable native oxide on the GaAs surface has been a main obstacle to realizing GaAs MOSFET owing to poor high-k/GaAs interface characteristics. Therefore, various surface passivation techniques prior to the deposition of high-k gate dielectric have been intensively studied, including Si [8], Ge [9], [10], ZnO [11], and Al 2 O 3 [12] as an interfacial passivation layer (IPL), surface passivation by sulfur compounds [13], and surface cleaning using hydrogen [14] or nitrogen plasma [15]. Depositing a thin layer of Al 2 O 3 before deposition of high-k dielectric can significantly improve the electrical characteristics of the GaAs MOS device [16], but its low k value (∼8) limits further device scaling.…”

Inversion-channel GaAs(100) metal-oxide-semiconductor field-effect-transistors using molecular beam deposited Al2O3 as a gate dielectric on different reconstructed surfaces

“…One exception has been the employment of ultra-highvacuum (UHV) deposited Ga 2 O 3 (Gd 2 O 3 ) 13 as a gate oxide on GaAs 8 and In 0.2 Ga 0.8 As, 14,15 in which D it spectra absent of the mid-gap peak and attainment of good drain currents were reported. Recently, some encouraging results have also been reported on GaAs MOS capacitors (MOSCAPs) or inversion-channel GaAs MOSFETs by employing Si interfacial passivation layer (IPL) technique [16][17][18] and GaAs (111)A crystalline orientation. 19 Significant enhancement of inversion currents has been demonstrated, indicating E f unpinning at oxide/GaAs interface.…”