Inversion-channel GaAs(100) metal-oxide-semiconductor field-effect-transistors using molecular beam deposited Al2O3 as a gate dielectric on different reconstructed surfaces

Abstract

Articles you may be interested inHigh-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effecttransistors by in-situ atomic-layer-deposited HfO2Low interfacial trap density and sub-nm equivalent oxide thickness in In0.53Ga0.47As (001) metal-oxidesemiconductor devices using molecular beam deposited HfO2/Al2O3 as gate dielectrics Appl. Phys. Lett. 99, 042908 (2011); 10.1063/1.3617436Self-aligned inversion-channel In 0.2 Ga 0.8 As metal-oxide-semiconductor field-effect transistor with molecular beam epitaxy Al 2 O 3 / Ga 2 O 3 ( Gd 2 O 3 ) as the gate dielectric J. Vac. Sci. Technol. B 29, 03C122 (2011); 10.1116/1.3565057 dc and rf characteristics of self-aligned inversion-channel In 0.53 Ga 0.47 As metal-oxide-semiconductor fieldeffect transistors using molecular beam epitaxy-Al 2 O 3 / Ga 2 O 3 ( Gd 2 O 3 ) as gate dielectricsInversion-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) have been fabricated using in-situ molecular beam deposited Al 2 O 3 as a gate dielectric directly on freshly molecular beam epitaxy grown Ga-stabilized (4 Â 6) and As-covered c(4 Â 4) GaAs(100) reconstructed surfaces. The MOSFET using the former surface gives a drain current (I d ) of 92 lA/l m and a transconductance (G m ) of 43 lS/lm in an 1 lm gate length configuration; these values are more than 100 times higher than those attained in the MOSFET using the latter surface, which has an I d of 0.47 lA/lm and a G m of 0.45 lS/lm. The enhancement of the inversion currents and G m may indicate Fermi-level unpinning at the oxide/GaAs(100) interface. The result further confirms that the mid-gap interfacial trap densities of 2 Â 10 12 eV À1 cm À2 and of exceeding 10 13 eV À1 cm À2 in the samples on the Ga-stabilized and the As-covered GaAs(100) surfaces, respectively, are correlated to the inversion-channel device performance. V C 2013 American Institute of Physics.

Reconstruction at the interface of one cycle of trimethylaluminum and water on GaAs(111)A-2×2 from atomic layer deposition

“…6) In contrast, symmetrical CVs for p-and n-GaAs(001) were observed by using in situ UHV-Ga 2 O 3 (Gd 2 O 3 ) on In 0.2 Ga 0.8 As(001)-4×2. 27) Also, for the molecular beam of deposited Al 2 O 3 on both p-and n-GaAs(001)-4×6, there were no "inversion-like" behavior in the CVs and QSCVs, 19) which is different from what we measured in ALD-Al 2 O 3 on GaAs(001) and (111)A.…”

“…17,18) The maximum drain current in the MOSFET on GaAs(111)A using atomic layer deposition (ALD) to grow rare earth oxides as the gate dielectrics is considerably greater than that in the MOSFET on GaAs(001). 17) However, under the condition of a similar gate length, the drain current of the device on GaAs(111)A is comparable to that of the MOSFETs on GaAs(001)-4×6 using molecular beam deposition (MBD)-Al 2 O 3 19) and molecular beam epitaxy (MBE)-Ga 2 O 3 (Gd 2 O 3 ). 20) These results indicate that the most critical issue affecting the performance of the devices is the nature of an interfacial chemical bonding that depends largely on the electronic structure of a semiconductor surface.…”

Atom-to-atom interactions for atomic layer deposition of trimethylaluminum on Ga-rich GaAs(001)-4 × 6 and As-rich GaAs(001)-2 × 4 surfaces: a synchrotron radiation photoemission study

“…The intensity of the As* component in the As-rich surface is greater than that in the Ga-rich surface. The greater intensity of the As* state in the GaAs(001) 2 × 4 surface results in a greater value of D it in the mid-gap and inferior device performances, as shown in [18] and [19], respectively.…”

Low interfacial trap density and high-temperature thermal stability in atomic layer deposited single crystal Y2O3/n-GaAs(001)

“…Inversion-channel GaAs(001) MOSFETs, nevertheless, have yet to produce comparable device results using the same gate dielectrics. [10][11][12] A "beyond Si" CMOS may consist of n-(In)GaAs and p-Ge (or p-GaSb) MOSFETs with a common gate dielectric and a CMOS compatible process, which requires high-temperature thermal stability and ALD-dielectrics. [13][14][15][16][17] The advantages of conformal coverage and the selflimiting nature in ALD have enabled its usage in depositing high-κ's in the semiconductor industry since the 45 nm node CMOS.…”