GaAs on 200 mm Si wafers via thin temperature graded Ge buffers by molecular beam epitaxy

The role of AsH3 partial pressure on anti-phase boundary in GaAs-on-Ge grown by MOCVD – Application to a 200mm GaAs virtual substrate

“…As shown in the cross-sectional TEM image (Figure 8), the interface between GaAs and Ge is free of crystalline defects, and no sign of anti-phase boundaries (APB) are detected in the GaAs layer. This compares favorably with a report of the latter structure grown by MBE, in which APB were detected at the GaAs/Ge interface [32]. The contrast at the Si/Ge interface is due to the abrupt relaxation of the 4.2% lattice mismatch creating an array of misfit dislocations.…”

Improvement of crystal quality and surface morphology of Ge/Gd2O3/Si(111) epitaxial layers by cyclic annealing and regrowth

“…In PGCA, the temperature of the samples was cycled 3 times at the end of the low-temperature growth, between 750 • C and 850 • C, and heat-soaked for 10 min at each of these temperatures. The PGCA recipe is similar to the one originally introduced by Luan et al [6] for Ge/Si(100) epitaxy, which successfully reduced the threading dislocation density (TDD) and improved the surface morphology in the original and subsequent works [31][32][33][34]. More recently, a systematic study by Yurasov et al has shown that PGCA between 725 • C and 850 • C, for 2-5 cycles and with heat-soaking for 2 min-6 min at each temperature, yielded a low TDD of the order of 10 7 cm −3 and root-mean-square (rms) roughness of <1 nm, in Ge/Si(001) epitaxial layers of sub µm thicknesses [32].…”

Heteroepitaxial Growth of III-V Semiconductors on Silicon

“…For the monolithic integration on Si platform, in general, a thin buffer layer is favorable in terms of thermal cracks [98] and co-integration with other components [12]. Although using thin Ge/GeSi buffer layers has been also demonstrated [165], the order of TDD (~10 8 cm −2 ) is much higher than that of thick Ge/GeSi or GaAs buffer layer (~10 6 cm −2 ). In addition, the chemical-mechanical polishing (CMP) process [164] used to obtain smooth surface in rough Ge/GeSi buffers can increase the fabrication cost and complexity.…”