Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCs

Reinbrecht, Cezar; Aljuffri, Abdullah; Hamdioui, Said; Taouil, Mottaqiallah; Forlin, Bruno; Sepúlveda, Johanna

doi:10.1109/isvlsi49217.2020.000-1

Cited by 8 publications

(9 citation statements)

References 30 publications

(35 reference statements)

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“…We will also discuss virtual prototyping, which can detect simple side channels. [100], Napoli2018 [101], Reinbrecht [102], De2019 [103], Zhang2018 [104], Dao2020 [105], Van2020 [106], Sauvage2017 [107].…”

Section: Protection Against Side-channel Attacksmentioning

confidence: 99%

“…Unfortunately, many current protection mechanisms are either platform-dependent or only effective against a few attacks. Reinbrecht [102] introduces Guard-NoC, which is a secure network-on-chip (NoC) architecture that can protect MPSoC from various Logical SCAs. The secure NoC uses three application-independent strategies to hide and isolate sensitive information by masking the execution time of the operation and employing dual communication strategy such as using packet and circuit switching at the same time.…”

Section: Timing Attackmentioning

confidence: 99%

“…European Processor Initiative (EPI), one of the cornerstones of the EuroHPC Joint Undertaking, a new European Union strategic entity focused on pooling the Union's and national resources on HPC to build and deploy the most powerful supercomputers within Europe, is preparing to adopt RISC-V as its core solution for exascale embedded HPC platform [9]. protection [54,56,57,59,61,[69][70][71][72], ISA security extensions [66,67,[73][74][75][76][77][78][79][80][81][82][83][84], cryptographic engines and primitives [78][79][80][81][82][83][85][86][87][88][89][90][91][92][93][94][95][96][97][98], and side-channel prevention [99][100][101]…”

Section: Introductionmentioning

confidence: 99%

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A Survey on RISC-V Security: Hardware and Architecture

2021

Preprint

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The Internet of Things (IoT) is an ongoing technological revolution. Embedded processors are the processing engines of smart IoT devices. For decades, these processors were mainly based on the Arm instruction set architecture (ISA). In recent years, the free and open RISC-V ISA standard has attracted the attention of industry and academia and is becoming the mainstream. Many companies have already owned or are designing RISC-V processors. Many important operating systems and major tool chains have supported RISC-V. Data security and user privacy protection are common challenges faced by all IoT devices. In order to deal with foreseeable security threats, the RISC-V community is studying security solutions aimed at achieving a root of trust (RoT) and ensuring that sensitive information on RISC-V devices is not tampered with or leaked. Many RISC-V security research projects are underway, but the academic community has not yet conducted a comprehensive survey of RISC-V security solutions. The latest technology and future development direction of RICS-V security research are still unclear. In order to fill this research gap, this paper presents an in-depth survey on RISC-V security technologies. This paper summarizes the representative security mechanisms of RISC-V hardware and architecture. Specifically, we first briefly introduce the background and development status of RISC-V, and compare the RISC-V mechanisms with the most relevant Arm mechanisms, highlighting their similarities and differences. Then, we investigate the security research of RISC-V around the theme of hardware and architecture security. Our survey covers hardware and physical access security, hardware-assisted security units, ISA security extensions, memory protection, cryptographic primitives, and side-channel attack protection. Based on our survey, we predict the future research and development directions of RISC-V security. We hope that our research can inspire RISC-V researchers and developers.CCS Concepts: • Security and privacy → Embedded systems security; Cryptography.

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Section: Protection Against Side-channel Attacksmentioning

confidence: 99%

Section: Timing Attackmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Survey on RISC-V Security: Hardware and Architecture

2021

Preprint

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“…In [100], authors have proposed an obfuscation module to add random delay to packets generated inside the static zone to protect them against timing attack and probing. Consequently, malicious IPs are no longer able to monitor the computation time and/or cache hit/miss rate of the target application.…”

Section: ) Static Secure Zonesmentioning

confidence: 99%

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

et al. 2021

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Network-on-Chips (NoCs) have been widely used as a scalable communication solution in the design of multiprocessor system-on-chips (MPSoCs). NoCs manage communications between on-chip Intellectual Property (IP) cores and allow processing cores to achieve higher performance by outsourcing their communication tasks. NoC paradigm is based on the idea of resource sharing where hardware resources, including buffers, communication links, routers, etc., are shared between all IPs of the MPSoC. In fact, the data being routed by each NoC router might not be related to the router's local core. Such a utilization-centric design approach can raise security issues in MPSoCs-based designs, e.g., integrity and confidentiality of the data being routed in an NoC might be compromised by unauthorized accesses/modifications of intermediate routers. Many papers in the literature have discovered and addressed security holes of NoCs, aiming at improving the security of the NoC paradigm. However, to the best of our knowledge, there is no solid survey study on the security vulnerabilities and countermeasures for NoCs. This paper will review security threats and countermeasures proposed so far for wired NoCs, wireless NoCs, and 3D NoCs. The paper aims at giving the readers an insight into the attacks and weaknesses/strengths of countermeasures.

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“…Reinbrecht et al [58] present Guard-NoC, a platform pro-tected against Side-Channel Attacks, specifically Timing Attacks. The protection is based on the Obfuscation Module (Figure 13), placed between the Network Interface and the local IC input.…”

Section: (V) Obfuscationmentioning

confidence: 99%

A Survey on Security Mechanisms for NoC-based Many-Core SoCs

Caimi

Faccenda

Moraes

2021

JICS

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The adoption of many-cores systems introduces the concern for data protection as a critical design requirement due to the resource sharing and the simultaneous executions of several applications on the platform. A secure application that processes sensitive data may have its security harmed by a malicious process. The literature contains several proposals to protect many-cores against attacks, focusing on the protection of the application execution or the access to shared memories. However, there is a gap to be fulfilled: a solution covering the entire application lifetime, including its admission, execution, and peripheral's access. This survey discusses three security-related issues: the secure admission of applications, the prevention of resource sharing during their execution, and the safe access to external devices. This survey concludes with an evaluation of the studied methods, pointing out directions and research opportunities.

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Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCs

Cited by 8 publications

References 30 publications

A Survey on RISC-V Security: Hardware and Architecture

A Survey on RISC-V Security: Hardware and Architecture

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

A Survey on Security Mechanisms for NoC-based Many-Core SoCs

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