A Survey on RISC-V Security: Hardware and Architecture

Abstract

The Internet of Things (IoT) is an ongoing technological revolution. Embedded processors are the processing engines of smart IoT devices. For decades, these processors were mainly based on the Arm instruction set architecture (ISA). In recent years, the free and open RISC-V ISA standard has attracted the attention of industry and academia and is becoming the mainstream. Many companies have already owned or are designing RISC-V processors. Many important operating systems and major tool chains have supported RISC-V. Data security and user privacy protection are common challenges faced by all IoT devices. In order to deal with foreseeable security threats, the RISC-V community is studying security solutions aimed at achieving a root of trust (RoT) and ensuring that sensitive information on RISC-V devices is not tampered with or leaked. Many RISC-V security research projects are underway, but the academic community has not yet conducted a comprehensive survey of RISC-V security solutions. The latest technology and future development direction of RICS-V security research are still unclear. In order to fill this research gap, this paper presents an in-depth survey on RISC-V security technologies. This paper summarizes the representative security mechanisms of RISC-V hardware and architecture. Specifically, we first briefly introduce the background and development status of RISC-V, and compare the RISC-V mechanisms with the most relevant Arm mechanisms, highlighting their similarities and differences. Then, we investigate the security research of RISC-V around the theme of hardware and architecture security. Our survey covers hardware and physical access security, hardware-assisted security units, ISA security extensions, memory protection, cryptographic primitives, and side-channel attack protection. Based on our survey, we predict the future research and development directions of RISC-V security. We hope that our research can inspire RISC-V researchers and developers.CCS Concepts: • Security and privacy → Embedded systems security; Cryptography.

RISC-V Instruction Set Architecture Extensions: A Survey

“…The work [12] gave a thorough survey of RISC-V security methods and provided a summary of the key security mechanisms of RISC-V, including side-channel attack resistance, control flow integrity strengthening, system attack surface reduction, etc. In addition to the research mentioned in [12], there are several new research on security ISA extension.…”

“…For artificial intelligence applications, works [6] and [7] proposed instruction set extensions for acceleration of deep learning algorithms. A lot of research is also being done on customising RISC-V instruction set extensions for high performance computing [8], graphics computing [9], communication [10], [11], security [12], and so on.…”

“…Even though a tremendous amount of study has been done, the research of RSIC-V ISA extension is still in its early stages, and we believe that both academics and industry professionals would benefit from a comprehensive survey. We have noticed that there are some early surveys [12]- [14] focused on RISC-V. The work [13] reviews the software support for RISC-V.…”

“…The work [13] reviews the software support for RISC-V. The work [12] presents an overview of RISC-V security technologies. The work [13] compares the different implementations of RISC-V processors.…”

SoK: Hardware-supported Trusted Execution Environments

“…There have been similar works that survey security mechanisms and TEEs in the RISC-V ecosystem. In [79], the author surveys hardware and architectural security for RISC-V processors and contrasts them to ARM processors. While this paper makes many good comparisons between the ARM and RISC-V architectures in general (e.g., exception levels) as well as with respect to security-related features (e.g., support for cryptography, ISA extensions), it only mentions that the Keystone architecture [35] is similar to ARM TrustZone but defers any further discussion to future work.…”