A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors
Jens Anders,
Pablo Andreu,
Bernd Becker
et al.
Abstract:With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the es… Show more
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