2000
DOI: 10.4028/www.scientific.net/msf.338-342.313
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Growth of Single Crystalline 3C-SiC and AIN on Si using Porous Si as a Compliant Seed Crystal

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Cited by 9 publications
(5 citation statements)
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“…In addition, the electron Hall mobility is isotropic and higher, compared with those of 4H-and 6H-polytypes, hence there is significant interest for synthesis of low-cost, large-size 3C-SiC wafers for microelectronic applications. Nevertheless, due to large differences in lattice constant (20%) and thermal expansion coefficient (8%) of the two materials, heteroepitaxy of SiC on Si substrate are reported to have high density of crystallographic structural defects such as stacking faults, microtwins, and inversion domain boundaries [15][16][17][18], however, the recent reports hint improvement of crystal quality by varying growth parameters such as substrate orientation and growth temperature etc, therefore the subject has got more interest amongst the researchers [19,20].…”
Section: Introductionmentioning
confidence: 99%
“…In addition, the electron Hall mobility is isotropic and higher, compared with those of 4H-and 6H-polytypes, hence there is significant interest for synthesis of low-cost, large-size 3C-SiC wafers for microelectronic applications. Nevertheless, due to large differences in lattice constant (20%) and thermal expansion coefficient (8%) of the two materials, heteroepitaxy of SiC on Si substrate are reported to have high density of crystallographic structural defects such as stacking faults, microtwins, and inversion domain boundaries [15][16][17][18], however, the recent reports hint improvement of crystal quality by varying growth parameters such as substrate orientation and growth temperature etc, therefore the subject has got more interest amongst the researchers [19,20].…”
Section: Introductionmentioning
confidence: 99%
“…Porous silicon (PS) can be used as such a compliant substrate. Some preliminary attempts of the 3C-SiC growth on the top of the porous silicon layer have been reported [2,3]. Unfortunately, in these papers the carbonization step was not considered properly.…”
Section: Introductionmentioning
confidence: 99%
“…For this reason most research is focused to improve the crystallographic properties and reduce the residual stress of the SiC layer. This can be achieved by using one of the following substrate modification methods: 1. reduction of the growth temperature by using high reactive carbon precursor and/or atomic layer epitaxial techniques [4][5][6][7][8][9][10][11][12][13][14], 2. use of silicon on insulator substrates [15], 3. application of SMART-CUT or wafer bonding technologies [16][17][18], 4. use of porous and nanostructured silicon [18][19][20], 5. modification of the silicon substrate with group IV elements [21][22][23][24]. Only the latter method is applicable if the electrical properties of the heterojunction are of interest.…”
Section: Introductionmentioning
confidence: 99%