Gradient-based optimization of custom circuits using a static-timing formulation

Conn, Andrew R.; Elfadel, Ibrahim M.; Molzen, W. W.; O'Brien, P.R.; Strenski, Philip N.; Visweswariah, Chandu; Whan, C.B.

doi:10.1145/309847.309979

Cited by 57 publications

(17 citation statements)

References 17 publications

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“…As a comparison, we also implemented the adder circuit with only 18 track cells. The optimization points of two adder implementations are obtained by running our in- house optimization tool with the same power-performance tradeoff range [14]. For each optimization point of the adder with only 18 track cells, we applied high V t optimization on its non-critical paths.…”

Section: Circuit Implementationmentioning

confidence: 99%

A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit

Zhang

Chan

Montoye

et al. 2009

J Sign Process Syst Sign Image Video Technol

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Section: Circuit Implementationmentioning

confidence: 99%

A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit

Zhang

Chan

Montoye

et al. 2009

J Sign Process Syst Sign Image Video Technol

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show abstract

“…In order to correct the error induced by the variation of fringe width, we used some statistical tools [21][22][23] to optimize the compressing rate. The basic gradient-based optimization tools will search the design space using a standard optimization algorithm until a point is reached at which the solution cannot be improved.…”

Section: Optimizing Compressing Ratementioning

confidence: 99%

Effect of defocused fringe on measured profile in structured line projection method

Song¹,

Jia²,

Ning³

et al. 2006

Interferometry XIII: Techniques and Analysis

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In industry, there are needs to accurately measure the 3-D profile of edges parts in order to evaluate edge condition. Optical methods are increasingly used for this purpose due to its advantages such as being noncontact, fast, accurate, and easy to integrate with software for data acquisition and feature analysis. We utilized structured line projection technology to measure edge's profile. In this method a structured light distribution, created by the transmission of a sinusoidal grating, was projected onto the inspected parts at a certain incidence angle. The projected light lines were deformed due to the depth change on the edge surface. A CCD camera sitting at a different angle was used to record the deformed fringes. From the deformed fringes the 3D surface profile was extracted based on triangulation principal. Because the projected grating pattern can be interpreted as an interference pattern, we used the spatial carrier phase shifting and phase unwrapping method as in classic interferometry to extract the phase information from the intensity distribution of fringes. Due to the limited depth-of-range of the fringe image and depth-offocus of the imaging lens on the CCD camera, the observed deformed fringes have different widths and frequencies at different depth. According to the definition of depth-of-focus, the fringe width out of focus can be on the order of the square root of 2 wider than that which is in focus. The width change can also be due to a tilt across the object. This width change affects the accuracy of the spatial carrier phase shifting and subsequently the accuracy of extracted profile. In this paper, we proposed to monitor the change of the fringe width with imaging depth. According to the width of the fringes, we defined a parameter called compressing rate, to use in computing the edge profile. For different edge types, the compressing rate was optimized in order to get the profile that can match the results from traditional the methods. By using this method, the system repeatability can be improved significantly.

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“…), gate sizings, supply voltages and threshold voltagesa large design space of possibilities. There exist a number of tools that can optimize a circuit along one or more of these circuit parameters to produce cost-performance tradeoff curves [6], [5], [14]. By trying a few discrete circuit topologies and circuit styles with these tools, one can construct the overall tradeoff space for a circuit [13].…”

Section: Introductionmentioning

confidence: 99%

An integrated framework for joint design space exploration of microarchitecture and circuits

Azizi

Mahesri

Stevenson

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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The design of a digital system for energy efficiency often requires the analysis of circuit tradeoffs in addition to architectural tradeoffs. To assist with this analysis, we present a framework for performing joint exploration of both the architectural and circuit design spaces. In our approach, we use statistical inference techniques to create a model of a large microarchitectural design space from a small number of simulation samples. We then characterize the design tradeoffs of each of the underlying circuits and integrate these with the higher level architectural models to define the joint circuit-architecture design space. We use posynomial forms for all our models, enabling the use of convex optimization tools to efficiently search the joint design space. As an example, we apply this methodology to explore the power-performance tradeoffs in a dual-issue superscalar out-of-order processor, showing how the framework can be used to determine the optimal set of design parameters for energy efficiency. Compared to current architectural tools that use fixed circuit costs, joint optimization can reduce energy by up to 30% by considering circuit tradeoff characteristics.

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Gradient-based optimization of custom circuits using a static-timing formulation

Cited by 57 publications

References 17 publications

A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit

A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit

Effect of defocused fringe on measured profile in structured line projection method

An integrated framework for joint design space exploration of microarchitecture and circuits

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