A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit

Theorem proving has been demonstrated as a powerful technique for datapath verification. This paper considers a generic logiclevel architecture of end-around-carry adder, which is extensively used in floating-point arithmetic. The architecture is component-based and parameterized for easy customization. The design architecture is formalized and verified in the mechanical theorem prover Coq. The scalable proof provides necessary underpinnings for verifying customized and new implementations. IndexTerms-Architecture, Coq, end-around-carry adder (EAC), floating-point unit (FPU), portable, theorem proving, verification.

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Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design

Wong

Betz

Rose

2014

IEEE Trans. VLSI Syst.

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Abstract-This paper compares the delay and area of a comprehensive set of processor building block circuits when implemented on custom CMOS and FPGA substrates, then uses these results to show how soft processor microarchitectures should be different from those of hard processors. We find that the ratios of the custom CMOS versus FPGA area for different building blocks varies considerably more than the speed ratios, thus, area ratios have more impact on microarchitecture choices. Complete processor cores on an FPGA use 17-27× more area ("area ratio") than the same design implemented in custom CMOS. Building blocks with dedicated hardware support on FPGAs such as SRAMs, adders, and multipliers are particularly area-efficient (2-7×), while multiplexers and content-addressable memories (CAM) are particularly area-inefficient (>100×). Applying these results, we find out-of-order soft processors should use physical register file organizations to minimize CAM size.

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A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit

Cited by 4 publications

References 16 publications

Formal Analysis of End-Around-Carry Adder in Floating-Point Unit

Formal Analysis of End-Around-Carry Adder in Floating-Point Unit

Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq

Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design

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