An integrated framework for joint design space exploration of microarchitecture and circuits

Azizi, Mohammad Hossein; Mahesri,; Stevenson, Freda K.; Patel, M. S.; Horowitz,

doi:10.1109/date.2010.5457204

Cited by 8 publications

(3 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Such predictive models might be trained with data from detailed circuit simulations and used for circuit tuning, statistical timing analysis, and Monte Carlo experiments to evaluate process variations. Early results in linking circuit and architecture models are promising [Azizi et al 2010;Liang et al 2009;Lovin et al 2009].…”

Section: Discussionmentioning

confidence: 99%

Applied inference

Lee

Brooks

2010

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

We propose and apply a new simulation paradigm for microarchitectural design evaluation and optimization. This paradigm enables more comprehensive design studies by combining spatial sampling and statistical inference. Specifically, this paradigm (1) defines a large, comprehensive design space, (2) samples points from the space for simulation, and (3) constructs regression models based on sparse simulations. This approach greatly improves the computational efficiency of microarchitectural simulation and enables new capabilities in design space exploration.We illustrate new capabilities in three case studies for a large design space of approximately 260,000 points: (1) Pareto frontier, (2) pipeline depth, and (3) multiprocessor heterogeneity analyses. In particular, regression models are exhaustively evaluated to identify Pareto optimal designs that maximize performance for given power budgets. These models enable pipeline depth studies in which all parameters vary simultaneously with depth, thereby more effectively revealing interactions with non-depth parameters. Heterogeneity analysis combines regression based optimization with clustering heuristics to identify efficient design compromises between similar optimal architectures. These compromises are potential core designs in a heterogeneous multicore architecture. Increasing heterogeneity can improve bips 3 /w efficiency by as much as 2.4x, a theoretical upper bound on heterogeneity benefits that neglects contention between shared resources as well as design complexity. Collectively these studies demonstrate regression models' ability to expose trends and identify optima in diverse design regions, motivating the application of such models in statistical inference for more effective use of modern simulator infrastructure.

show abstract

Section: Discussionmentioning

confidence: 99%

Applied inference

Lee

Brooks

2010

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

show abstract

“…With respect to VLSI design, DSE is becoming a more attractive solution for complex problems across various levels of abstraction. At the architectural level, many DSE studies based on models or simulators have been used to explore multi-objective design spaces, e.g., [10]. Architecturallevel studies, however, typically do not result in implemented designs.…”

Section: Related Workmentioning

confidence: 99%

Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors

Ziegler

Liu

Carloni

2016

Proceedings of the 2016 International Symposium on Low Power Electronics and Design

View full text Add to dashboard Cite

Modern logic and physical synthesis tools provide numerous options and parameters that can drastically impact design quality; however, the large number of options leads to a complex design space difficult for human designers to navigate. By employing intelligent search strategies and parallel computing we can tackle this parameter tuning problem, thus automating one of the key design tasks conventionally performed by a human designer. In this paper we present a novel learning-based algorithm for synthesis parameter optimization. This new algorithm has been integrated into our existing autonomous parameter-tuning system, which was used to design multiple 22nm industrial chips and is currently being used for 14nm chips. These techniques show, on average, over 40% reduction in total negative slack and over 10% power reduction across hundreds of 14nm industrial processor macros while reducing overall human design effort. We also present a new higher-level system that manages parameter tuning of multiple designs in a scalable way. This new system addresses the needs of large design teams by prioritizing the tuning effort to maximize returns given the available compute resources.

show abstract

“…Notice that most previous works optimize the target design as a whole entity [3], but this joint-optimization approach has limited scalability with complex SoC designs. While some works have system-composition properties [5,11], the CAPS approach is uniquely efficient in sampling components only when is required.…”

Section: Related Workmentioning

confidence: 99%