Globally asynchronous locally synchronous micropipelined processor implementation in FPGA

Optimising Self-Timed FPGA Circuits

“…Mapping synchronous logic to asynchronous structure may not map efficiently and there has been no indication that the core asynchronous fabric on these devices can be utilised for asynchronous design. 3) Mapping asynchronous logic to synchronous FPGA fabric [5], [6], [7]. This has been treated with caution This work was sponsored by Thales Optronics Ltd and the Engineering and Physical Sciences Research Council (EPSRC) under the Engineering Doctorate (EngD) programme due to the overhead in attempting to make components within clocked device and their inherent hazards conform to the hazard free design requirements of asynchronous logic design.…”

“…Most have opted for a delay insensitive encoding scheme to absorb the delay variation at the expense of resources. In recent times there have been a few research projects [7], [8], [9] that have followed variations of the third approach to produce asynchronous implementations of small 5 stage pipeline RISC processors. Marshall [9] began from an asynchronous gate level description and converted each gate into the equivalent Xilinx primitive block.…”

“…Although both projects were modest in their achievements, both used a reasonably similar approach of creating a primitive translation to convert ASIC components into the equivalent gate netlist suitable for FPGA synthesis. Zafar [7] created another 5 stage RISC processor but with a targeted micropipeline suitable for FPGA implementation. The authors used a dual-rail encoding mechanism which is truly delay insensitive, however this consumes a significant amount of FPGA resources.…”