Optimising Self-Timed FPGA Circuits

Abstract

This paper introduces a novel synchronous to asynchronous logic conversion tool targeted specifically for a synchronous field programmable gate array (FPGA). This tool augments the synchronous FPGA design flow and removes the clock network to implement an asynchronous control network in its place. We evaluate the timing performance benefits of the methods used to implement the asynchronous control network on synchronous FPGA fabric. Industrial video processing circuits are used to demonstrate the iterative timing improvements the tool makes to asynchronous control networks in each circuit. The targeted design constraints used in the tool are intended to improve the robustness and predictability of the placed circuits. This allows the timing benefits of asynchronous bundled data circuits easier to achieve, making asynchronous circuits a viable design option on modern FPGAs.

Self-timed circuits FPGA implementation flow

“…The slack definitions that we have compared in Section II show that implementing self-timed circuits in FPGAs cannot be directly handled with the conventional synchronous approach. To get around this obstacle, we proposed a new methodology that reuses the ideas of incremental synthesis and partitioning, introduced in [4] and [6], in a more generic way targeting modern FPGAs fabrics and tools. To the best of our knowledge, all the work we have found on implementing self-timed circuits in FPGAs only deal with the worst-case delay constraint.…”

“…Many techniques have been used to alleviate this limitation. They vary according to the asynchronous design approach adopted in the system of interest and to the evolution of the FPGA fabric and tools [4]- [6].…”

“…The method described in [6] uses delay elements to duplicate the worst case delay of the combinational block in an asynchronous pipeline stage. They use incremental synthesis and implementation to iteratively alter delay elements until they match the delay of the logic.…”

Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

“…Along the given applications, another impressive approach called continuous‐time digital signal processing requires matched delay lines, which include voltage‐controlled adjustable delay cells . Furthermore, the delay elements that are not controllable in run‐time but exhibit low deviation act the fundamental role in time‐multiplexing pulse capture devices and promising new techniques for synchronous logic to asynchronous logic conversion . The common key property is the stability of the delay for the aforementioned examples.…”