Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs

Dal, M.J.H. van; Vellianitis, G.; Doornbos, G.; Duriez, B.; Holland, M.; Vasen, T.; Afzalian, Aryan; Chen, E.; Su, Sheng-Kai; Chen, Ta-Kun; Shen, Ting; Zheng, Wei; Diaz, C.H.

doi:10.1109/iedm.2018.8614577

Cited by 34 publications

(12 citation statements)

References 16 publications

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“…Due to the improved gate control and band gap widening by QCE, the IOFF of the Si0.8Ge0.2 UT-FinFET was effectively decreased. Fig.4 shows the electron effective mobility as a function of inversion carrier density (Ninv) which is extracted from equation 3to (6). The peak mobility values of Si0.8Ge0.2 UT-FinFET and Si FinFET are 138 and 80 (cm 2 /V-s) respectively.…”

Section: Resultsmentioning

confidence: 99%

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio

Sun

Tsai

Yan

et al. 2020

IEEE J. Electron Devices Soc.

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We successfully fabricate the Si0.8Ge0.2 channel fin field-effect-transistor (FinFET) with 5 nm ultra-thin fin width and high aspect ratio (~10×) on silicon-on-insulator (SOI) substrate by simple two-step dry etching. In comparison of the conventional Si FinFET, our proposed SiGe ultra-thin FinFETs (Si0.8Ge0.2 UT-FinFET) at VD = 0.75 V & VG = 1.5 V shows higher ON-state current (1 mA/fin), even achieve lower OFF-state current (0.2 nA/fin) and steep subthreshold slope (SS) of 76 mV/decade, which is owing to the better gate control given by the ultra-thin fin channel. In addition, this work also exhibits the suppression of short channel effect (SCE) with very small drain induced barrier-lowering (DIBL) of 4 mV/V.

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Section: Resultsmentioning

confidence: 99%

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio

Sun

Tsai

Yan

et al. 2020

IEEE J. Electron Devices Soc.

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“…19), achieving a low ρ c has been specifically challenging due to the high Schottky barrier height, limited solubility of dopants, and Fermi level pinning. The ρ c of n-Ge has been continuously improved for the past decade, and the best value is 1.6×10 −9 -cm 2 [122] while there are multiple papers that report ∼ 10 −8 -cm 2 . For p-Ge (Fig.…”

Section: Discussion: Effects Of Contact Resistivitymentioning

confidence: 99%

“…And then, we use R c = ρ c /L conact × 2, where L contact is the contact length, and the factor 2 arises because R c includes effects of both source and drain. In this discussion, we assume L contact = 8 nm In the Appendix, as a supplementary approach to discuss the effect of material-dependent ρ c , we provide another CV 2 vs. CV/I plot using R SD estimated from the best experimental ρ c reported in literatures for each material [55], [122], [134], [135] (also see Figs. 18-20).…”

Section: Discussion: Effects Of Contact Resistivitymentioning

confidence: 99%

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Comprehensive n- and pMOSFET Channel Material Benchmarking and Analysis of CMOS Performance Metrics Considering Quantum Transport and Carrier Scattering Effects

Kim

Avci

Young

2020

IEEE J. Electron Devices Soc.

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Comprehensive channel material benchmarking for n-and pMOS are performed considering effects of quantum transport and carrier scattering. Various channel material options (Si, InAs, In 0.7 Ga 0.3 As, In 0.53 Ga 0.47 As, GaAs, and Ge for nMOS, Si and Ge for pMOS) are covered using hybrid simulation of quantum ballistic transport and semi-classical Monte Carlo. Current-voltage characteristics and performance metrics such as the capacitance and effective drive current (I eff) are explored considering device parasitic components. For low power operation, III-V nMOS may deliver good performance while Ge n-and pMOS with different source/drain tip designs may give performance advantage over Si from low power to high performance operations. CMOS benchmarking results for I eff , capacitance, and switching energy vs. delay (for gate capacitance loading vs. interconnect wire capacitance loading) are also presented for various homogeneous and hybrid combinations of n-and pMOS (Si CMOS, III-V hybrid CMOS, Ge hybrid CMOS, and Ge CMOS). Finally, sensitivity analysis is performed for I eff on the parasitic resistance (R SD) and contact resistivity (ρ c). Novel channel materials may relax the R SD and ρ c requirements to match the I eff performance of Si reference. Comprehensive literature reviews of experimental ρ c 's of novel materials are also presented to discuss the effect of material-dependent R SD .

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“…In addition, in order to obtain a larger drive current, the channel mobility should be improved. It is also a development trend to use higher mobility SiGe and Ge materials instead of silicon [15,16]. The diameter of nanowires or pillars significantly affects the performance of the device.For sensors, a small size diameter will raise sensitivity because of the higher surface-to-volume ratio [17,18].…”

Section: Introductionmentioning

confidence: 99%

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

Zhou

et al. 2020

Materials

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Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.

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Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs

Cited by 34 publications

References 16 publications

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio

Comprehensive n- and pMOSFET Channel Material Benchmarking and Analysis of CMOS Performance Metrics Considering Quantum Transport and Carrier Scattering Effects

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

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Ge CMOS gate stack and contact development for Vertically Stacked Lateral Nanowire FETs

Cited by 34 publications

References 16 publications

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio

Comprehensive n- and pMOSFET Channel Material Benchmarking and Analysis of CMOS Performance Metrics Considering Quantum Transport and Carrier Scattering Effects

A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm

Contact Info

Product

Resources

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Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio

Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High I_ON/I_OFF Ratio