Comprehensive n- and pMOSFET Channel Material Benchmarking and Analysis of CMOS Performance Metrics Considering Quantum Transport and Carrier Scattering Effects

Abstract

Comprehensive channel material benchmarking for n-and pMOS are performed considering effects of quantum transport and carrier scattering. Various channel material options (Si, InAs, In 0.7 Ga 0.3 As, In 0.53 Ga 0.47 As, GaAs, and Ge for nMOS, Si and Ge for pMOS) are covered using hybrid simulation of quantum ballistic transport and semi-classical Monte Carlo. Current-voltage characteristics and performance metrics such as the capacitance and effective drive current (I eff) are explored considering device parasitic components. For low power operation, III-V nMOS may deliver good performance while Ge n-and pMOS with different source/drain tip designs may give performance advantage over Si from low power to high performance operations. CMOS benchmarking results for I eff , capacitance, and switching energy vs. delay (for gate capacitance loading vs. interconnect wire capacitance loading) are also presented for various homogeneous and hybrid combinations of n-and pMOS (Si CMOS, III-V hybrid CMOS, Ge hybrid CMOS, and Ge CMOS). Finally, sensitivity analysis is performed for I eff on the parasitic resistance (R SD) and contact resistivity (ρ c). Novel channel materials may relax the R SD and ρ c requirements to match the I eff performance of Si reference. Comprehensive literature reviews of experimental ρ c 's of novel materials are also presented to discuss the effect of material-dependent R SD .

Monolithically Cointegrated Tensile Strained Germanium and InxGa1-xAs FinFETs for Tunable CMOS Logic

“…However, layer transfer and wafer bonding are expensive and thus, the large-scale integration of logic devices proves to be challenging in terms of voids, wafer alignment, cost, and density [9]. On the other hand, InGaAs on oxide-on-insulator (OI), InAs-OI, Ge-OI and SiGe-OI based transistors have been studied through simulations [10], [11] and experiment [7], [12]. The growth of such semiconductor layers on -OI wafers pose an issue of thermal conductivity mismatch that can results in defects, cracks, and un-intentional strain on the active layers.…”