Monolithically Cointegrated Tensile Strained Germanium and In_xGa_1-xAs FinFETs for Tunable CMOS Logic

Abstract

In this paper, we have evaluated the merits of monolithically co-integrated alternate channel CMOS device architecture, utilizing tensile strained germanium (𝜺-Ge) for the pchannel FinFET and variable indium (In) compositional InxGa1-xAs (0.10 ≤ x ≤ 0.53) for the n-channel FinFET. The device simulation models were calibrated using the experimental results of Ge and InGaAs FinFETs, and subsequently transferred to the co-integrated Ge and InxGa1-xAs structure while keeping the device simulation parameters fixed. The device parameters such as VT, ION, IOFF, and SS were determined for identical fin dimensions for n-and p-channel FinFETs as a function of In composition that alters the tensile strain in Ge. These parameters are controllable during the heteroepitaxial growth by varying In composition in InxGa1-xAs. 𝜺-Ge p-FinFET is shown to be superior in terms of SS and ION/IOFF ratio compared to other competing architectures. The co-integrated architecture of CMOS inverter exhibited an optimum performance over a range of In compositions from 20 % to 40 % while driving fan-out FO-1 and FO-4 load configurations.In addition, the CMOS inverter with symmetric rise and fall times as well as noise-immune functionality demonstrated 150 GHz of operating frequency with 30 nW total power dissipation at 20% In composition, and hence a superior power-delay-product comparable to ITRS standards. Moreover, the 3-stage CMOS ring oscillator performance was evaluated with various In compositions to be stable and power efficient. Thus, the co-integrated approach has a potential to (i) simplify large scale CMOS integration, and (ii) be compatible with optoelectronic materials.

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

“…1(a) shows the Ge FinFET structure used to calibrate the simulation model [16]. The details of the structure and simulation model are provided elsewhere [15]. Fig.…”

“…NSFET B utilizes the same geometry with an alternate gate stack (GeO x /Al 2 O 3 /HfO 2 /Metal), where the higher dielectric constant of Al 2 O 3 compared to SiO 2 is expected to provide improved electrostatic control. Strain (compressive or tensile) in p-NSFET channels is expected to improve the hole mobility [5], [6], [10] but tensile strain can prove to be more beneficial due to dominance of LH-valley over HH [15], [21]. Fig.…”

“…1c) which utilizes a Ge/In x Ga 1x As/AlAs pseudomorphic stack to introduce the tensile strain in -Ge [21]. This tensile strain can be controlled using the In composition in the In x Ga 1-x As layer [15] [21]. The details of the In composition dependent tunable tensile strain and effect of strain on -Ge transistor/circuit performance is reported earlier [15].…”

“…This tensile strain can be controlled using the In composition in the In x Ga 1-x As layer [15] [21]. The details of the In composition dependent tunable tensile strain and effect of strain on -Ge transistor/circuit performance is reported earlier [15]. Although, the height of the NSFET C is limited by the critical layer thickness of -Ge (similar to strained Si in Si/SiGe system and Ge in Ge/SiGe) thus restricting the number of stacked layers, the benefits of high hole-mobility of Ge as well as mobility boost due to tensile strain in Ge may prove to be an acceptable trade-off.…”

“…Post etching, the intermediate structure is indistinguishable from conventional Ge NSFET, except for the virtually defect-free channel. Here, we have introduced three novel NSFET architectures based on Ge/III-V material systems and analyzed their performance metrics and design considerations for 0.5 V CMOS using TCAD simulations, based on experimentally calibrated [15], [16] and re-validated [17] simulation models.…”