Ge channel MOSFETs directly on silicon

Chen, Che Wei; Chung, Chia-Jung; Chien, Chia-Hung

doi:10.1109/edssc.2014.7061261

2014 IEEE International Conference on Electron Devices and Solid-State Circuits 2014

DOI: 10.1109/edssc.2014.7061261

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Ge channel MOSFETs directly on silicon

Che Wei Chen

Chia-Jung Chung

Chia-Hung Chien

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2018

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Ge-cap quantum-well bulk FinFET for 5 nm node CMOS integration

Kurniawan¹,

Peng²,

Yang³

et al. 2018

Jpn. J. Appl. Phys.

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We propose the use of Ge-cap quantum-well (QW) bulk FinFET for 5 nm CMOS integration, which is a Si channel wrapped with Ge around three sides of the fin channel. The simulation results show that the Ge-cap FinFET structure demonstrates better performance than pure Si, pure Ge, and Si-cap FinFET structures. By optimizing Si fin width and Ge-cap thickness, the on-state current of nFET and pFET can also be symmetric without changing the total fin width (F Wp = F Wn ). The electrons in Ge-cap nFinFET concentrate in the Si channel because of QWs formed in the lowest conduction band of the Ge and Si heterostructure, while the holes in Ge-cap pFinFET prefer to stay in Ge surfaces owing to QWs formed in the Ge valence band. The physics studies of this device have made the design rules relevant for the application of the CMOS inverter and static random access memory (SRAM) application technology.

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Ge-cap quantum-well bulk FinFET for 5 nm node CMOS integration

Kurniawan¹,

Peng²,

Yang³

et al. 2018

Jpn. J. Appl. Phys.

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show abstract

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Ge channel MOSFETs directly on silicon

Cited by 1 publication

References 4 publications

Ge-cap quantum-well bulk FinFET for 5 nm node CMOS integration

Ge-cap quantum-well bulk FinFET for 5 nm node CMOS integration

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