Gate Sizing For Cell Library-Based Designs

Ketkar, Mahesh; Hu, Jinglu

doi:10.1109/dac.2007.375282

Cited by 10 publications

(33 citation statements)

References 3 publications

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“…These works ignore the fact that most cell library-based designs have discretized gate sizes. Later, some rounding techniques have been proposed to map the continuous solutions to the discrete grid [14]. More recently, Liu and Hu [15] proposed to use dynamic-programming style algorithms for solving discretized gate sizing problem directly.…”

Section: Gate Sizingmentioning

confidence: 99%

Shedding Physical Synthesis Area Bloat

Zhou

Alpert

et al. 2011

VLSI Design

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Area bloat in physical synthesis not only increases power dissipation, but also creates congestion problems, forces designers to enlarge the die area, rerun the whole design flow, and postpone the design deadline. As a result, it is vital for physical synthesis tools to achieve timing closure and low power consumption with intelligent area control. The major sources of area increase in a typical physical synthesis flow are from buffer insertion and gate sizing, both of which have been discussed extensively in the last two decades, where the main focus is individual optimized algorithm. However, building a practical physical synthesis flow with buffering and gate sizing to achieve the best timing/area/runtime is rarely discussed in any previous literatures. In this paper, we present two simple yet efficient buffering and gate sizing techniques and achieve a physical synthesis flow with much smaller area bloat. Compared to a traditional timing-driven flow, our work achieves 12% logic area growth reduction, 5.8% total area reduction, 10.1% wirelength reduction, and 770 ps worst slack improvement on average on 20 industrial designs in 65 nm and 45 nm.

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Section: Gate Sizingmentioning

confidence: 99%

Shedding Physical Synthesis Area Bloat

Zhou

Alpert

et al. 2011

VLSI Design

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“…Due to the increasing complexity of design rule checking, this approach will rather expand with decreasing feature sizes. Often such libraries are too sparse to allow for fast and simple nearest rounding [10]. In [10] a dynamic programming approach for improved rounding was proposed, but its running time will be rather too high for large designs.…”

Section: Introductionmentioning

confidence: 99%

“…Often such libraries are too sparse to allow for fast and simple nearest rounding [10]. In [10] a dynamic programming approach for improved rounding was proposed, but its running time will be rather too high for large designs. In fact, an efficient rounding procedure providing a quality guarantee is not yet known.…”

Section: Introductionmentioning

confidence: 99%

Gate sizing for large cell-based designs

Held¹

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices and realistic timing models. The approach iteratively assigns signal slew targets to all source pins of the chip and chooses discrete layouts of minimum size preserving the slew targets. Using slew targets instead of delay budgets, accurate estimates for the input slews are available during the sizing step. Slew targets are updated by an estimate of the local slew gradient.To demonstrate the effectiveness, we propose a new heuristic to estimate lower bounds for the worst path delay. On average, we violate these bounds by 6%. A subsequent local search decreases this gap quickly to 2%. This two-stage approach is capable of sizing designs with more than 5.8 million cells within 2.5 hours and thus helping to decrease turn-around times of multi-million cell designs.

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“…It is common to simplify circuit delay models and solve an abstract, continuous version of the problem to facilitate convex optimization -Lagrangian relaxation, linear programming, network flows, etc. [6,10,20,21,25]. Simultaneous gate sizing and V th assignment has shown promising results [23,24].…”

Section: Introductionmentioning

confidence: 99%

High-performance gate sizing with a signoff timer

Kahng

Kang

Lee

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Process and device scaling in late-CMOS technologies highlight leakage power as a critical challenge for the semiconductor industry. Careful gate sizing and V th -swapping can reduce leakage, but prior optimizations based on convex or dynamic programming (i) are often based on unrealistic assumptions about circuit delay and slew propagation, (ii) fail to handle practical design rules such as transition time or load upper bounds, and (iii) do not scale well to input complexities when full extracted parasitics are available. Seeing substantial opportunities for improvement, we present a multithreaded, stochastic optimization (Trident2.0) for gate sizing and V th assignment to minimize leakage power subject to capacitance, slew and timing constraints. Scalability and high performance of Trident2.0 are validated on ISPD-2013 Gate Sizing Contest benchmarks.

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Gate Sizing For Cell Library-Based Designs

Cited by 10 publications

References 3 publications

Shedding Physical Synthesis Area Bloat

Shedding Physical Synthesis Area Bloat

Gate sizing for large cell-based designs

High-performance gate sizing with a signoff timer

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