Gate sizing for large cell-based designs

Abstract

Abstract-Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices and realistic timing models. The approach iteratively assigns signal slew targets to all source pins of the chip and chooses discrete layouts of minimum size preserving the slew targets. Using slew targets instead of delay budgets, accurate estimates for the input slews are available during the sizing step. Slew targets are updated by an estimate of the local slew gradient.To demonstrate the effectiveness, we propose a new heuristic to estimate lower bounds for the worst path delay. On average, we violate these bounds by 6%. A subsequent local search decreases this gap quickly to 2%. This two-stage approach is capable of sizing designs with more than 5.8 million cells within 2.5 hours and thus helping to decrease turn-around times of multi-million cell designs.

Delay Optimization of Combinational Logic by AND-OR Path Restructuring

“…Depending on the actual stage of the design, our detailed optimization step invokes buffering, layer assignment and gate sizing tools. When used in late physical design, we apply Held's gate sizing routine [9], followed by the buffering tool with an integrated layer assignment by Bartoschek et al [2]. After buffering, we apply gate sizing again, in particular on newly inserted buffers.…”

Local search algorithms for timing-driven placement under arbitrary delay models

“…In addition, the load capacitance of the nets on the critical path can be reduced by moving less critical downstream cells closer to the path. To accomplish this uniformly for all gates, regardless if they lie on a critical path or not, we use the local slack metric from [10]:…”

High-performance gate sizing with a signoff timer

“…Instead, we interface with the signoff tool using a Tcl-socket interface, similar to the one in UCSD SensOpt [22]. 5 Our interface is illustrated in Figure 5, including client-server Tcl socket code [31].…”

“…Simultaneous gate sizing and V th assignment has shown promising results [23,24]. Some industry work emphasizes discrete methods [5], including dynamic programming [16] that assumes structural properties of delay functions that do not quite hold in practice. Device physics imply nonconvex delay functions, causing nonconvexities in SPICE results and nonlinear delay Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”