Local search algorithms for timing-driven placement under arbitrary delay models

Bock, Adrian; Held, Stephan; Kämmerling, Nicolas; Schorr, Ulrike

doi:10.1145/2744769.2744867

Cited by 11 publications

(3 citation statements)

References 29 publications

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“…It can be noticed that when the path-length-based factor is removed from Eqn. (19) for global packing, the runtime will significantly increase since there are many zigzag critical paths which will cost a lot of runtime for detailed placement to handle them. According to the results of Cfg5, using small square windows without sector-windows can also increase the runtime since these narrow windows slow down the optimization progress of the critical paths.…”

Section: B Comparison With Vivadomentioning

confidence: 99%

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

Liang¹,

Chen²,

Zhao³

et al. 2022

Preprint

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To enable the performance optimization of application mapping on modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable macros with constraints of shape and resources lead to challenging mixed-size placement for FPGA designs which cannot be addressed by previous analytical placers. Moreover, general timing-driven placement algorithms are facing challenges when handling real-world application design and ultrascale FPGA architectures. In this work, we propose AMF-Placer 2.0, an open-source comprehensive timing-driven Analytical Mixed-size FPGA placer. It supports mixed-size placement of heterogeneous resources (e.g., LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM) on FPGA, with an interface to Xilinx Vivado. To speed up the convergence and improve the timing quality of the placement, standing upon the shoulders of AMF-Placer 1.0, AMF-Placer 2.0 is equipped with a series of new techniques for timing optimization, including a simple but effective timing model, placement-blockage-aware anchor insertion, WNS-aware timing-driven quadratic placement, and sector-guided detailed placement. Based on a set of the latest large open-source benchmarks from various domains for Xilinx Ultrascale FPGAs, experimental results indicate that critical path delays realized by AMF-Placer 2.0 are averagely 2.2% and 0.59% higher than those achieved by commercial tool Xilinx Vivavo 2020.2 and 2021.2 respectively. Meanwhile, the average runtime of placement procedure of AMF-Placer 2.0 is 14% and 8.5% higher than Xilinx Vivavo 2020.2 and 2021.2 respectively. Although limited by the absence of the exact timing model of the device, the information of design hierarchy and accurate routing feedback, AMF-Placer 2.0 is the first open-source FPGA placer which can handle the timingdriven mixed-size placement of practical complex designs with various FPGA resources and achieves the comparable quality to the latest commercial tools.

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Section: B Comparison With Vivadomentioning

confidence: 99%

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

Liang¹,

Chen²,

Zhao³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…In this formulation, Lagrangian multipliers indicate weights of critical timing nets. In [101], timing violations are optimized with timing path straightening and cell clustering movement techniques. In [101], the Euclidean distance of outer pins in critical nets is shortened to reduce wire length and timing propagation in critical timing nets.…”

Section: B Timing-driven Detailed Placementmentioning

confidence: 99%

“…In [101], timing violations are optimized with timing path straightening and cell clustering movement techniques. In [101], the Euclidean distance of outer pins in critical nets is shortened to reduce wire length and timing propagation in critical timing nets. In [102], Steiner tree branches which are free of timing violations, are shortened to minimize the wire load capacitance of critical timing nets.…”

Section: B Timing-driven Detailed Placementmentioning

confidence: 99%

VLSI Placement Optimization Algorithms

Monteiro

2022

JICS

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Placement is a fundamental optimization step to compute cell locations. The quality of results in Clock Tree Synthesis (CTS) and routing stages is impacted by the placement solution. The placement optimization flow is split into (1)global placement, (2) legalization, and (3) detailed placement. In global placement, cell locations are computed to minimize total wire length subject to a maximum cell density threshold. The cell overlapping and cell alignment to site row boundaries are relaxed. In legalization, cells are placed in locations free of overlapping and aligned to site row boundaries. Legalization algorithms compute cell locations with minimized cell displacement. In detailed placement, objectives are optimized locally. Detailed placement algorithms iterate over one cell or a small set of cells. The traditional optimization objective is total wire length. Placement algorithms also address timing violations, routability, design rules, and so forth. The placement algorithms rely on heuristics and formal methods to compute optimized cell locations. Moreover, placement algorithms require models to address signal delay propagation, area density, routing congestion, hyper-edge nets, and so forth. In the literature, several algorithms have been presented to improve placement solutions. On the other hand, placement is a really challenging problem that continues to have space for further improvement and for innovative algorithms.

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Quadratic timing objectives for incremental timing-driven placement optimization

Fogaça

Flach

Monteiro

et al. 2016

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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Local search algorithms for timing-driven placement under arbitrary delay models

Cited by 11 publications

References 29 publications

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

VLSI Placement Optimization Algorithms

Quadratic timing objectives for incremental timing-driven placement optimization

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