The best method known for determining lower bounds on the vertex coloring number of a graph is the linear-programming column-generation technique, where variables correspond to stable sets, first employed by Mehrotra and Trick in 1996. We present an implementation of the method that provides numerically-safe results, independent of the floating-point accuracy of linear-programming software. Our work includes an improved branch-andbound algorithm for maximum-weight stable sets and a parallel branch-andprice framework for graph coloring. Computational results are presented on a collection of standard test instances, including the unsolved challenge problems created by David S. Johnson in 1989.
In this paper we present a new method for clock scheduling and clocktree construction that improves the performance of high-end ASICs significantly.First, we compute a clock schedule that yields the optimum cycle time and the best possible clock distribution with respect to early and late mode; in particular the number of critical tests is minimized. Second, individual arrival time intervals are computed for all endpoints of the clocktree. Finally, we construct a clocktree that realizes arrival times within these intervals and exploits positive slacks to save power consumption.We demonstrate the superiority of our method to previous approaches by experimental results on industrial ASICs with up to 194 000 registers and more than 160 clock domains. We improved the clock frequencies by 5-28% up to 1.033 GHz (in hardware).
We consider the problem of constructing fast and small parallel prefix adders for nonuniform input arrival times. This problem arises whenever the adder is embedded into a more complex circuit, e. g. a multiplier.Most previous results are based on representing binary carry-propagate adders as so-called parallel prefix graphs, in which pairs of generate and propagate signals are combined using complex gates known as prefix gates. Adders constructed in this model usually minimize the delay in terms of these prefix gates. However, the delay in terms of logic gates can be worse by a factor of two.In contrast, we aim to minimize the delay of the underlying logic circuit directly. We prove a lower bound on the delay of a carry bit computation achievable by any prefix carry bit circuit and develop an algorithm that computes a prefix carry bit circuit with optimum delay up to a small additive constant. Furthermore, we use this algorithm to construct a small parallel prefix adder.Compared to existing algorithms we simultaneously improve the delay and size guarantee, as well as the running time for constructing prefix carry bit and adder circuits.
We study the minimum rectilinear Steiner tree problem in the presence of obstacles. Traversing obstacles is not strictly forbidden, but the total length of each connected component in the intersection of the tree with the interior of the blocked area is bounded by a constant. This problem is motivated by the layout of repeater tree topologies, a central task in chip design. Large blockages might be crossed by wires on higher layers, but repeaters may not be placed within the blocked area. A too long unbuffered piece of interconnect would lead to timing violations.We present a 2-approximation algorithm with a worst case running time of O((k log k) 2 ), where k is the number of terminals plus the number of obstacle corner points. Under mild assumptions on the obstacle structure, as they are prevalent in chip design, the running time is O(k(log k) 2 ). Compared to strictly obstacle-avoiding trees, the algorithm provides significantly shorter solutions. It solves real world instances with 783 352 terminals within 126 seconds, proving its practical applicability.
We present a very fast algorithm for topology generation of repeater trees. Based on the criticality of the individual sinks, which is estimated taking their required signal arrival times and their distance from the root of the repeater tree into account, this topology connects very critical sinks in such a way as to maximize the minimum slack and to minimize wiring for non-critical sinks.We establish theoretical bounds on the optimum solution and prove that our algorithm produces results that are close to optimum with respect to slack and wirelength. Experimental results on industrial designs in 130 nm and 90 nm technologies demonstrate the excellent quality of our algorithm. Moreover, one million nontrivial repeater tree topologies are constructed in less than one minute of computing time.
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