Abstract-Even with the wide adaptation of resolution enhancement techniques in sub-wavelength lithography, the geometry of the fabricated interconnect is still quite different from the drawn one. Existing Layout Parasitic Extraction (LPE) tools assume perfect geometry, thus introducing significant error in the extracted parasitic models, which in turn cases significant error in timing verification and signal integrity analysis. Our simulation shows that the RC parasitics extracted from perfect GDS-II geometry can be as much as 20% different from those extracted from the post litho/etching simulation geometry. This paper presents a new LPE methodology and related fast algorithms for interconnect parasitic extraction under photolithographic effects. Our methodology is compatible with the existing design flow. Experimental results show that the proposed methods are accurate and efficient.

Accurate chip level timing analysis requires a careful modeling of interaction between logic drivers and interconnect wires. Existing static-timing analysis methodologies translate the actual loading and interconnect parasitics into a single effective capacitance. However, previous approaches to perform that translation capture the delay information only. They are not able to capture the slew information at the output of logic drivers, which results in unnecessary inaccuracy for static timing analysis. This paper presents a new accurate and simple closedform approach to compute the effective capacitance and model the slew rate at the signal output more accurately. Our approach is especially suitable for the chip level timing analysis at the early stage of design.

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