A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects

Abstract

Abstract-Even with the wide adaptation of resolution enhancement techniques in sub-wavelength lithography, the geometry of the fabricated interconnect is still quite different from the drawn one. Existing Layout Parasitic Extraction (LPE) tools assume perfect geometry, thus introducing significant error in the extracted parasitic models, which in turn cases significant error in timing verification and signal integrity analysis. Our simulation shows that the RC parasitics extracted from perfect GDS-II geometry can be as much as 20% different from those extracted from the post litho/etching simulation geometry. This paper presents a new LPE methodology and related fast algorithms for interconnect parasitic extraction under photolithographic effects. Our methodology is compatible with the existing design flow. Experimental results show that the proposed methods are accurate and efficient.

A Stochastic Algorithm Based on Fast Marching for Automatic Capacitance Extraction in Non-Manhattan Geometries

“…Physically, this is due to the larger overlap of the electrodes in the second set and to the spikes in the electric field close to sharp corners. The same effect has been reported in more complicated, 3D simulations [23]. In general, the capacitances for submicron structures are highly dependent on process geometry especially for multidielectric technologies.…”

“…, n P edge pixels p j := p EDGE Γ k | j are picked on the edge of Γ k according to (24); the command edge can be used for this task. They lead to the footpoint guesses {z 0 j } according to (23) and, by (22), to the footpoints {z j }. Now, χ k can be constructed on them if the footpoints are ordered sequentially (but not necessarily equispaced) along the level set ψ E = −h around Γ k .…”

Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation

“…With the poly size getting smaller in Figure 5, TDVC becomes more and more serious, so TDVC modeling parameter tvcr is scalable with W to describe this global effect in Equation 10. In TDVC modeling process, vco, vcw, vcn, tvw and tvo are fitting parameters: (9) tvo W tvw tvcr (10) The fitting result of TDVC modeling in P + /N + non-silicide poly-silicon resistor is shown in Figure 10. All silicon data and simulation are normalized by R T0 to make the fitting result clearly.…”

“…However, they are always traditionally simulated by field-solver. Due to some process variation such as etching [7], erosion [8] and optical proximity correction (OPC) [9], the field-solver simulation data loses accuracy without real silicon verification.…”

Variational capacitance modeling using orthogonal polynomial method

“…In this paper, we investigate the geometry variational impacts on the extracted capacitance. Statistical extraction of capacitance considering process variations has been studied recently and several approaches have been proposed [7,18,4,19,17] under different variational models. Method in [7], uses analytical formulae to consider the variations in capacitance extraction and it has only first-order accuracy.…”