A More Effective Ceff for Slew Estimation

Abstract

Accurate chip level timing analysis requires a careful modeling of interaction between logic drivers and interconnect wires. Existing static-timing analysis methodologies translate the actual loading and interconnect parasitics into a single effective capacitance. However, previous approaches to perform that translation capture the delay information only. They are not able to capture the slew information at the output of logic drivers, which results in unnecessary inaccuracy for static timing analysis. This paper presents a new accurate and simple closedform approach to compute the effective capacitance and model the slew rate at the signal output more accurately. Our approach is especially suitable for the chip level timing analysis at the early stage of design.

Novel techniques for timing analysis of VLSI circuits in advanced technology nodes

“…In fact, most related works are either computationally expensive or unable to approximate the driver output slew, which is essential in timing analysis since it also impacts interconnect delay and slew estimation. Furthermore, they require additional non-standard precharacterization and ignore the impact of Miller effect on C e f f and driver output waveform [7][8][9][10][11][12][13][14][15].…”

“…Therefore, it allows for variable analysis resolution exploiting an accuracy/runtime trade-off, enabling applicability to both optimization steps and signoff timing analysis. In contrast to prior works [7][8][9][10][11][12][13][14][15], our approach is compatible with industrial CSMs and considers the impact of Miller capacitance. Experimental results on representative stages implemented in 7 nm Fin Field-Effect Transistor (FinFET) technology indicate that our method achieves 1.3% and 2.5% delay and slew error against SPICE, respectively.…”

“…To overcome this limitation, many works propose the use of a single or two C e f f values for matching the output slew directly [10,11,14] or matching specific output voltage thresholds (e.g., 10% and 50%) separately [13]. In [10], authors compute a single C e f f by tuning an osculating Thevenin model, until the delay when the model is loaded by the original RC interconnect and the delay when the model is loaded by C e f f are approximately equal.…”

“…On the other hand, modeling the complex RC network using total interconnect capacitance (C total ) is overly pessimistic, due to the resistive shielding effect [7]. For accurate gate delay estimation, previous approaches [7][8][9][10][11][12][13][14][15] compute an effective capacitance (C e f f ) to account for resistive shielding, while maintaining compatibility with precharacterized gate models. However, most of these approaches, whether iterative [7,[9][10][11][12]14,15] or non-iterative [8,13], are either computationally expensive or inadequate to approximate the output slew.…”

“…For accurate gate delay estimation, previous approaches [7][8][9][10][11][12][13][14][15] compute an effective capacitance (C e f f ) to account for resistive shielding, while maintaining compatibility with precharacterized gate models. However, most of these approaches, whether iterative [7,[9][10][11][12]14,15] or non-iterative [8,13], are either computationally expensive or inadequate to approximate the output slew. Moreover, they require explicit instantiation of a Thevenin equivalent gate model, as well as precharacterization of information that is not part of standard cell libraries.…”