Gate Circuit Layout Optimization of Power Module Regarding Transient Current Imbalance

A fast universal power module layout method

“…Boundary element method based parasitic parameter calculation is utilized for fitness evaluation in [6] and it is the main cause for low speed with a large die number. To increase the optimization speed, the current conducting length is used to represent parasitic resistance and the surrounded area is used to represent the parasitic inductance [5]. The best routing results will be passed to outer loop at the end of inner loop iterations.…”

“…The conventional manual layout design procedures are usually based on design iterations [3][4][5]. Each cycle can generate a layout design result, which can then be compared with other design results.…”

Improvement of GaN transistors working conditions to increase efficiency Of A 100W DC-DC converter

“…A large parasitic inductance on the driving circuit causes slow load of the C ISS capacitance (for the gate circuit) of the transistor and also slows power commutations down. A fast gate drive is useless if the layout design is not optimized (parasitic elements too large) [7]. The efficiency computations did no take into account these speed limitations due to the stray inductances.…”

Layout optimization of power modules using a sequentially coupled approach

“…In the design of such multidisciplinary products, layout must be optimized because it acts on both electrical and thermal performance. Layout consists in connecting semi-conductors (transistors and diodes also called chips), to external pins by using Direct Bonded Copper (DBC) tracks and wire bondings [1]. These connecting elements have electrical resistances, inductances and capacitances that can have parasitic effects on the power module.…”