Abstract:The layout of power modules is one of the key points in power module design, especially for high power densities, where couplings are increased. In this paper, along with the design example, a fast and universal layout design method for both wirebond and planar power modules is presented. Some practical considerations and implementations are introduced in the optimization of module layout design.
“…Since high speed switching is required for this module, power terminals and gate signal terminals are bonded to DBC with ultrasonic bonding methods to reduce parasitic parameters. The next step is layout design, and a genetic algorithm (GA) based layout optimization in [12] is utilized to generate a high performance design. The design space of the module layout is fully searched.…”
“…Since high speed switching is required for this module, power terminals and gate signal terminals are bonded to DBC with ultrasonic bonding methods to reduce parasitic parameters. The next step is layout design, and a genetic algorithm (GA) based layout optimization in [12] is utilized to generate a high performance design. The design space of the module layout is fully searched.…”
“…However, the SP method becomes slower and much more complicated when the number of components increases over 10. In [9], typical elements were listed and interpreted for a planar modules, as shown in Fig.3. The DBC is not divided in small regions.…”
“…However, the DNA interpretation in [9] is still not simple enough for SiC planar module with a large number of dies. To speed up the positioning procedure, only 3 types are left, as switches, diodes and power terminals.…”
“…In [8] and [9], an automatic design methods by using genetic algorithms (GA) were invented and introduced by the same author of this paper. With this automatic methods, layout A design spaces can be better searched and optimized without any human interruption.…”
The layout of power modules is one of the key points in power module design, especially for silicon carbide module, which may parallel more devices compared with silicon counterpart. In this paper, along with the design example, a improved layout design method for planar power modules is presented. Some practical considerations and implementations are also introduced in the optimization of module layout design.
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